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Considering a single CPU and 4 stages of pipeline

Now after some time Instruction fetch,Instruction Decode,Execute,Store is running parellely means overlapping . Thats why we are getting one instructions executed per clk cycle.[ideally]

Now my doubt is how pipeline stage overlapping is possible with single cpu. As all stages may need CPU inorder to perform their task.

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A processor (a core) is not a different entity.For example this above 5 stage pipeline datapath is built inside a typical processor which enables the system to run overlapping instruction. The control unit synchronizes all stage operations. On a particular common clock pulse the control unit activates control signals and depending on which each stage do it's functionality. Make sure that here, the processor is not fetching more than one instrutions simultaneously.(superscalar processor is irrelevent in our case).

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