0 votes 0 votes In 2's complement addition, Overflow is flagged whenever there is carry from sign bit addition can not occur when a positive value is added to a negative value is flagged when the carries from sign bit and previous bit match none of the above Digital Logic digital-logic go-digital-logic-1 number-representation + – Bikram asked Sep 20, 2016 Bikram 406 views answer comment Share Follow See all 2 Comments See all 2 2 Comments reply Shivam Chauhan commented Sep 23, 2016 reply Follow Share Thanks for this question : seethis 0 votes 0 votes mcjoshi commented Sep 23, 2016 i edited by mcjoshi Oct 6, 2016 reply Follow Share Yes, answer given in GO2017-Digital for this question is wrong. Answer should be (B) not (C) @Arjun+Suresh+1 @Arjun Please correct this 2 votes 2 votes Please log in or register to add a comment.
0 votes 0 votes answer should b B. Tushar Pal 1 answered Oct 1, 2016 Tushar Pal 1 comment Share Follow See all 0 reply Please log in or register to add a comment.