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The following sequence of instruction is executed in a basic 5 stage pipelined processor (S1, S2, S3, S4, S5). Assume that data dependency present in the program is resolved by operand forwarding techniques. Load instruction output present in 4th stage ALU instruction output is available in 3rd stage. Assume each stage take 1 cycle.

What is the number of instructions must be inserted to achieve CPI = 1 by using operand forwarding.

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3 STALLS if resource conflict is resolved by renaming.

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The question is very tricky, you don't need anything special here, you just need to revise the definition of CPI and when do CPI get equals to 1.

According to question even if you use renaming technique or any technique, there will be 3 stalls for sure.

But " successful characteristics of a pipeline is in every new cycle, new input must be inserted into a pipeline therefore cpi=1".

So you can see even if there are 3 stalls but in every new cycle one new instruction get inserted so the answer would be 5.

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