Counter

Question

4-bit 16 module ripple counter uses JK-flip flop.propagation delay of each flip flop is 50ns find max clock frequncy.

Comments

why but??

from 0000 to 0001 only one flip flop has been changed  so only 50ns is sufficient rt??

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Yes you are correct but we are taking 4-bit ripple counter 0000 to 1111  thus when when the counter moves from 1111 to 0000 it has to update all flip flops and signal to flow from all flip flops so at worst case we need to take all flip flops otherwisw uneven output will occur at later part of counting

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Video Solution: https://youtu.be/S7iUh6vbtis 

Answer 1

Every clock pulse (either negative edge or positive edge ) should come as >= total propagation delay

Time period of clock >= 4*50ns      // asynchronous counter

Fmax <= 1/(4*50*10^(-9))          // asynchronous counter

Fmax <=  5MHz

 we are taking 4-bit ripple counter 0000 to 1111  thus when  the counter moves from 1111 to 0000 it has to update all flip flops and signal to flow from all flip flops so at worst case we need to take all flip flops otherwise uneven output will occur at later part of counting

Comments

is for each count it require 200ns ??

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Yes for each count it has to pass through the 4 flip flops hence the overall delay = 50 * 4 ns

Hence clock frequency = 1/200 ns = 5 MHz