When Clear input is low (since active low signal) , the output of the flipflop is reset to 0, independent of clock pulse.
Look at the diagram LSB == Q0 AND MSB = Q3
When the NAND gate output is zero then flipflop is reset independent of clock pulse.
But NAND gate output is Zero only when both inputs are 1.
Inputs of NAND gate are connected to Q3 and Q2 ==> Q3=1,Q2=1,Q1=0,Q0=0
MOD-12 counter states are 0,1,2,3,4,5,6,7,8,9,10,11.