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Consider the following circuit with initial state $Q_0 = Q_1 = 0$. The D Flip-flops are positive edged triggered and have set up times 20 nanosecond and hold times $0.$

Consider the following timing diagrams of X and C. The clock period of $C \geq 40$ nanosecond. Which one is the correct plot of Y?

      

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55 votes

Answer is (a).

Given clock is $+$ edge triggered. 

See the first positive edge. $X$ is $0$, and hence, the output is $0$. $Q_0$ is $0$ and $Q_0'$ is $1$. 

Second $+$ edge, $X$ is $1$ and $Q_0'$ is also $1.$ So, output is $1.$ (When second positive edge of the clock arrives, $Q_0'$ would surely be $1$ because the setup time of flip-flop is given as $20$ ns and the clock period is $\geq 40$ $ns$)

Third $+$ edge, $X$ is $1$ and $Q_0'$ is $0,$ So, output is $0.$ $(Q_0'$ becomes $0$ before the third positive edge, but output $Y$ would not change as the flip-flop is positive edge triggered)

Now, output never changes back to $1$ as $Q_0'$ is always $0$ and when $Q_0'$ finally becomes $1, X$ is $0.$ 

Set up time and hold times are given just to ensure that edge triggering works properly.

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Setup Time

Minimum amount of time BEFORE the clock's active edge that the data must be stable for it to be latched correctly

Hold Time

Minimum amount of Time AFTER the clock's active edge during which data must be stable

  • Setup and Hold time measured with respect to active clock edge

Read This

  • Initial state 
           $Q_0=Q_1=0$ (given)
           Setup Time   = 20ns
           Hold Time    = 0ns
           Clock Period = 40ns
  • Behaviour of Flip Flp depends on setup time and hold time
  • Flip Flop responds to the input during +ve edge but it consider the stable input which was given even before setup time
  • Flip-Flop changes its output to stable state within hold time
     

  • Above input will not be considered in the immediate +ve edge but it will be considered in the next coming +ve edge
  • In our Question $\color{Red} X$ goes to $0\rightarrow1$ before stable time which get considered in the immediate +ve edge

  • From the truth table it is clear that $Q_1$ is HIGH at $ \color{Blue}{ \text{clock } 1}$ only

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Modifications or corrections to the timing diagram are welcomed.

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