GATE CSE 2001 | Question: 2.8

Question

Consider the following circuit with initial state $Q_0 = Q_1 = 0$. The D Flip-flops are positive edged triggered and have set up times 20 nanosecond and hold times $0.$

Consider the following timing diagrams of X and C. The clock period of $C \geq 40$ nanosecond. Which one is the correct plot of Y?

      

• A.
• B.
• C.
• D.

Answer 1

answer - C

initially Q₀' is 1

for the first clock period nothing will change since input doesn't come before rising edge of the clock cycle

Q₀' will only go to 0 on rising edge of next clock cycle

for only one clock cycle D1 will be 1 and hence Y

Comments

But once Q1 becomes 1 it should become 0 only on the next rising edge of clock rt? That is after an entire clock period as in option (A)