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+26 votes

Consider the following circuit with initial state $Q_0 = Q_1 = 0$. The D Flip-flops are positive edged triggered and have set up times 20 nanosecond and hold times 0.

Consider the following timing diagrams of X and C. The clock period of $C \geq 40$ nanosecond. Which one is the correct plot of Y?

+30 votes

Best answer

Answer is (a)

Given clock is + edge triggered.

See the first positive edge. X is 0, and hence the output is 0. Q_{0} is 0 and Q_{0}' is 1.

Second + edge, X is 1 and Q_{0}' is also one. So, output is 1. (When second positive edge of the clock arrives, Q_{0}' would surely be 1 because the setup time of flip-flop is given as 20 ns and the clock period is >= 40 ns)

Third + edge, X is 1 and Q_{0}' is 0, So, output is 0. (Q_{0}' becomes 0 before the 3rd positive edge, but output Y won't change as the flip-flop is positive edge triggered)

Now, output never changes back to 1 as Q_{0}' is always 0 and when Q_{0}' finally becomes 1, X is 0.

Set up time and hold times are given just to ensure that edge triggering works properly.

0

Sir why on 2nd positive edge Q0' is 1....

At 2nd +ve edge, X is 1. So Output Q0 will be 1 and Q0' should be 0.

Please explain a bit more...

At 2nd +ve edge, X is 1. So Output Q0 will be 1 and Q0' should be 0.

Please explain a bit more...

–2

Yes. But X is at input only. Only when clock is active, flip flop produces output. i.e., until clock is active and the flip flop output is produced, $Q_0'$ will remain the old value.

+1

We are talking about output at 2nd +ve edge. 2nd +ve edge means Clock was active at that time, otherwise, we would not have said '2nd +ve edge of clock'.... and what is Setup time of Flip Flop means

0

At all instants the two inputs of AND gate, X and Q_{0}^{' }will be compliments of each other. Then how can the D_{1 }input and hence Y become 1?

0

Characteristic equation for D flip fop is:

Q_{n+1}=D

But from the solution given by you, it seems you are using

Q_{n+1}=D'

+3

I also found something...

Setup time is defined as the minimum amount of time before the clock's active edge that the data must be stable for it to be latched correctly.

Hold time is defined as the minimum amount of time after the clock's active edge during which data must be stable.

Setup time is defined as the minimum amount of time before the clock's active edge that the data must be stable for it to be latched correctly.

Hold time is defined as the minimum amount of time after the clock's active edge during which data must be stable.

0

Sir option A is right. But shouldn't the pulse width be more??? Bcoz it is falling even before we are getting 3 rd clk trnsition. And since it is +ve edge triggered it should change outputs only on +ve egdes and for remaining time it must hold output right???

0

@arjun sir, @praveen sir

please tell me where to study the theory to solve these timing diagram related questions ?

please tell me where to study the theory to solve these timing diagram related questions ?

+30 votes

**Setup Time**

Minimum amount of time BEFORE the clock's active edge that the data must be stable for it to be latched correctly

**Hold Time**

Minimum amount of Time AFTER the clock's active edge during which data must be stable

- Setup and Hold time measured with respect to active clock edge

Read This

- Initial state

$Q_0=Q_1=0$ (given)

Setup Time = 20ns

Hold Time = 0ns

Clock Period = 40ns - Behaviour of Flip Flp depends on setup time and hold time
- Flip Flop responds to the input during +ve edge but it consider the stable input which was given even before setup time
- Flip-Flop changes its output to stable state within hold time

- Above input will not be considered in the immediate +ve edge but it will be considered in the next coming +ve edge
- In our Question $\color{Red} X$ goes to $0\rightarrow1$ before stable time which get considered in the immediate +ve edge

- From the truth table it is clear that $Q_1$ is
**HIGH**at $ \color{Blue}{ \text{clock } 1}$ only

+17 votes

0

Hi @tanaya ji, Thanks for valuable effort.

Notice change appears in $Q_{0}$ and $Q_{1}$ when clock is positively triggered. But $D_{1}$ does not depend on clock triggering(means $D_{1}$ can change any time if it's I/P changes).

0

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