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Consider the following circuit with initial state $Q_0 = Q_1 = 0$. The D Flip-flops are positive edged triggered and have set up times 20 nanosecond and hold times 0.

Consider the following timing diagrams of X and C. The clock period of $C \geq 40$ nanosecond. Which one is the correct plot of Y?

asked in Digital Logic by Veteran (59.6k points)
edited by | 4.3k views

4 Answers

+30 votes
Best answer

Answer is (a).

Given clock is $+$ edge triggered. 

See the first positive edge. $X$ is $0$, and hence, the output is $0$. Q0 is $0$ and Q0' is $1$. 

Second + edge, X is $1$ and Q0' is also one. So, output is 1. (When second positive edge of the clock arrives, Q0' would surely be $1$ because the setup time of flip-flop is given as $20$ ns and the clock period is $>= 40$ $ns$)

Third $+$ edge, $X$ is $1$ and Q0' is 0, So, output is 0. (Q0' becomes 0 before the 3rd positive edge, but output Y won't change as the flip-flop is positive edge triggered)

Now, output never changes back to 1 as Q0' is always 0 and when Q0' finally becomes 1, X is 0. 

Set up time and hold times are given just to ensure that edge triggering works properly.

answered by Veteran (363k points)
edited by
+1
hi can you please explain why output never changes back ow Q0' is 1 on second + edge
0
Sir how is Q` 0 inthird edge.. It is 1 right/
0
I have edited the answer- now it should be clear.
+1
Sir why on 2nd positive edge Q0' is 1....

At 2nd +ve edge, X is 1. So Output Q0 will be 1 and Q0' should be 0.

 

Please explain a bit more...
–1
Yes. But X is at input only. Only when clock is active, flip flop produces output. i.e., until clock is active and the flip flop output is produced, $Q_0'$ will remain the old value.
+1
We are talking about output at 2nd +ve edge. 2nd +ve edge means Clock was active at that time, otherwise, we would not have said '2nd +ve edge of clock'.... and what is Setup time of Flip Flop means
0

At all instants the two inputs of AND gate, X and Q0' will be compliments of each other. Then how can the D1 input and hence Y become 1?

0

Characteristic equation for D flip fop is:

Qn+1=D

But from the solution given by you, it seems you are using

Qn+1=D'

0
@Arjun sir...Why setup time and hold time are important here, what is the significance?
+3
I also found something...

Setup time is defined as the minimum amount of time before the clock's active edge that the data must be stable for it to be latched correctly.

Hold time is defined as the minimum amount of time after the clock's active edge during which data must be stable.
0
Sir option A is right. But shouldn't the pulse width be more??? Bcoz it is falling even before we are getting 3 rd clk trnsition. And since it is +ve edge triggered it should change outputs only on +ve egdes and for remaining time it must hold output right???
0
@arjun sir,  @praveen sir

please tell me where to study the theory to solve these timing diagram related questions ?
0

Third + edge, X is 1 and Q0' is 0, So, output is 0. (Q0' becomes 0 before the 3rd positive edge, but output Y won't change as the flip flop is positive edge triggered)

how  Q0'  is 0 here,in third clock?

0
sir first +ve edge of clock why not Q0=0??
0

how Q0 is 1 in first line??

0
yes, it is 0 -- corrected now.
0
more explanation required.....
0

Second + edge, X is 1 and Q0' is also one. So, output is 1. (When second positive edge of the clock arrives, Q0' would surely be 1 because the setup time of flip-flop is given as 20 ns and the clock period is >= 40 ns)

@Arjun Sir Why the qo' is 1 in second +ve edge. Please explain it more briefly.

0
@arjun sir it's required more explanation
+48 votes

Setup Time

Minimum amount of time BEFORE the clock's active edge that the data must be stable for it to be latched correctly

Hold Time

Minimum amount of Time AFTER the clock's active edge during which data must be stable

  • Setup and Hold time measured with respect to active clock edge

Read This

  • Initial state 
           $Q_0=Q_1=0$ (given)
           Setup Time   = 20ns
           Hold Time    = 0ns
           Clock Period = 40ns
  • Behaviour of Flip Flp depends on setup time and hold time
  • Flip Flop responds to the input during +ve edge but it consider the stable input which was given even before setup time
  • Flip-Flop changes its output to stable state within hold time
     

  • Above input will not be considered in the immediate +ve edge but it will be considered in the next coming +ve edge
  • In our Question $\color{Red} X$ goes to $0\rightarrow1$ before stable time which get considered in the immediate +ve edge

  • From the truth table it is clear that $Q_1$ is HIGH at $ \color{Blue}{ \text{clock } 1}$ only

answered by Boss (22.4k points)
edited by
+3
@pC in truth table , for clock=1 , D1=D0.(Q0)'=1.0=0 plz verify
+3

Btw clock 0 and Clock 1 ===> the i/p of D1 changed to 1 ( due to AND gate shows immediate effect )

after applying the Clock 1 ===> Q0 =1 and Q1 = 1

 

Btw clock 1 and Clock 2 ===> the i/p of D1 changed to 0

after applying the Clock 2 ===> Q0 =1 and Q1 = 0

 

Btw clock 2 and Clock 3 ===> the i/p of D1 is 0

after applying the Clock 3 ===> Q0 =1 and Q1 = 0

 

etc

0
thanks

very clear explanation :)
+30 votes

Modifications or corrections to the timing diagram are welcomed.

answered by Junior (645 points)
0

Hi @tanaya ji, Thanks for valuable effort. 

Notice change appears in $Q_{0}$ and $Q_{1}$ when clock is positively triggered. But  $D_{1}$ does not depend on clock triggering(means $D_{1}$ can change any time if it's I/P changes). 

0
Can you specify the gaps??
0
Each FF has a delay of 20ns so output at Y gets delayed by 20ns as depicted in the timing diagram.
0
(Q0)' will not change during the last change of X from high to low, as before the last +ve edge of the clock , X changed during the setup time(20ns) whereas signal should be constant during setup time for output to be guranteed.
0
this should be best answer
–1 vote

answer - C

initially Q0' is 1

for the first clock period nothing will change since input doesn't come before rising edge of the clock cycle

Q0' will only go to 0 on rising edge of next clock cycle

for only one clock cycle D1 will be 1 and hence Y

answered by Loyal (9.1k points)
+1
But once Q1 becomes 1 it should become 0 only on the next rising edge of clock rt? That is after an entire clock period as in option (A)
Answer:

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