62 votes 62 votes Consider the following circuit with initial state $Q_0 = Q_1 = 0$. The D Flip-flops are positive edged triggered and have set up times 20 nanosecond and hold times $0.$ Consider the following timing diagrams of X and C. The clock period of $C \geq 40$ nanosecond. Which one is the correct plot of Y? Digital Logic gatecse-2001 digital-logic circuit-output normal + – Kathleen asked Sep 14, 2014 • edited Jul 16, 2019 by ajaysoni1924 Kathleen 21.5k views answer comment Share Follow See all 0 reply Please log in or register to add a comment.
0 votes 0 votes answer - C initially Q0' is 1 for the first clock period nothing will change since input doesn't come before rising edge of the clock cycle Q0' will only go to 0 on rising edge of next clock cycle for only one clock cycle D1 will be 1 and hence Y ankitrokdeonsns answered Oct 20, 2014 ankitrokdeonsns comment Share Follow See 1 comment See all 1 1 comment reply Arjun commented Nov 3, 2014 reply Follow Share But once Q1 becomes 1 it should become 0 only on the next rising edge of clock rt? That is after an entire clock period as in option (A) 1 votes 1 votes Please log in or register to add a comment.