GATE CSE 2001 | Question: 2.13

Question

Consider the following data path of a simple non-pipelined CPU. The registers $A, B$, $A_{1},A_{2}, \textsf{MDR},$ the $\textsf{bus}$ and the $\textsf{ALU}$ are $8$-$bit$ wide. $\textsf{SP}$ and $\textsf{MAR}$ are $16$-$bit$ registers. The $\textsf{MUX}$ is of size $8 \times (2:1)$ and the $\textsf{DEMUX}$ is of size $8 \times (1:2)$. Each memory operation takes $2$ $\textsf{CPU}$ clock cycles and uses $\textsf{MAR}$ (Memory Address Register) and $\textsf{MDR}$ (Memory Date Register). $\textsf{SP}$ can be decremented locally.

The $\textsf{CPU}$ instruction "push r" where, $r =$ $A$ or $B$ has the specification

• $M[SP] ← r $
• $SP ← SP - 1$

How many $\textsf{CPU}$ clock cycles are required to execute the "push r" instruction?

• A. $2$
• B. $3$
• C. $4$
• D. $5$

Comments

Can anyone share any resource or link to solve such kind of ALU data path question except previous years gate question. It will be very helpful

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using sachin Sir explaination on this  Question https://gateoverflow.in/43568/gate2005-80.  .

I got the Answer 2.

Explaination;

T0: MAR← SP   (SINCE THERE IS A CONNECTION BETWEEN MUX OF SP AND DEMUX OF MAR I ASSUME THIS TRANSFER DOES NOT USE INTERNAL BUS.)

T0: MDR← R ( THIS USES INTERNAL BUS)

T1: SP<-SP-1 (LOCAL)   

T1: M[MAR]<-MDR

 

Can somebody clarify if this is right?

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There is typo in question.

MDR (Memory Date Register)

Shouldn’t it be Memory Data Register?

Answer 1

Excuse me for bad handwriting.

Answer 2

Video solution is given below

Answer 3

1. Fetch Instruction: (1 cycle)

   • Retrieve the instruction "push r" from memory.

2. Decode and Read Register r: (1 cycle)

   • Decode the instruction to determine which register (A or B) to push.
   • Read the value from the specified register r.

3. Memory Write: (2 cycles)

   • Load the value from r into the MDR (Memory Data Register).
   • Transfer the content of SP to MAR (Memory Address Register).
   • Write the value from MDR to memory at the address specified by MAR.

4. Decrement SP: (1 cycle)

   • Subtract 1 from the value in the SP (Stack Pointer) register.

Therefore, the entire "push r" instruction requires 1 + 1 + 2 + 1 = 5 CPU clock cycles to complete.