Minimum number of two input NAND gates required to realize the logic circuit

Question

The truth table for the combinational circuit is shown below:

What is the minimum number of two input NAND gates required to realize this logic circuit?

Comments

Is it coming 7?

Answer 1

here we realise K-map then we get Y= A' B'+B'C'+ A'C'

  so its AND-OR realization so  three NAND gate use for A', B',C' and  4 NAND gate for AND-OR so total 7 NAND gate is required.

Comments

Y can also be written as Y = B'(A' + C') + A'C' = B'(AC)' + A'C' = [(B'(AC)')' (A'C')']'

It can be implemented in just 4 NAND gates.

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@amit here use 4 NAND gate but A', B', C' how to generate so that's why i use 3 more NAND gate as generate  A',B',C' ...

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amit is correct, we have to arrive at [(B'(AC)')' (A'C')']' which then can be implemented with seven "2 input" NANDs.

Answer 2

By simplifying the expression for Y we get

Y = A' (B' + C')

Implementing (B' + C') or (BC)' will require 1 NAND gate. Implementing A' will require another NAND gate. Combining the output of the previous two, we will get (A' (BC)')' = A + BC. Again feeding it into a NAND gate will give (A + BC)' = A' + (B' + C') = Y.

Hence, 4 NAND gates required in total.

Answer 3

7 NAND gates.

Expression after minimization

=B'C' + A'C' + A'B'

= B'C' + A'(C' + B')

=B'C' + A'(BC)'

Now, for the SOP expression, 3 NAND gates.

Additionally, 1 NAND to realise (BC)'

 1 NAND to realise to C'

 1 NAND to realise to B'

 1 NAND to realise to A'