TLB is a cache specially designed for page table mappings. Each entry in the TLB has the two basic fields: a tag field , a data field which is the size of the physical page number (pointer to that location), and several bits that indicate the status of the TLB line or of the page associated with it. These bits usually are a dirty bit which indicates if the corresponding page has been written, a reference bit which indicates if the corresponding page has been accessed, and a write protection bit which indicates if writes are allowed in the corresponding page.
At every memory reference the TLB is accessed with the virtual page number field of the virtual address. If there is a hit (hit can be said only by looking $\color{green}{valid-bit = 1}$), then, TLB (Hardware) returns frame no. of the frame where the page is present If there is a miss in the TLB (this is also called translation), the control must determine if there is a real page fault or a simple TLB miss.
TLB miss can be quickly resolved by updating the TLB entry with the proper information from the page table residing in main memory. In the case of a page fault the CPU gets interrupted, and the interrupt handler will take the necessary steps to service the fault.
PS:) Page fault refers to the scenario where the obtained translation cannot be effectively used. It may be a missing page or a dirty page or access permission mismatch. So, a TLB hit can still lead to a page fault.