#operating system

Question

True or False : if there is Hit in TLB than there won't be page fault ??

Give reason

Comments

We match tags when we lookup for some page in TLB, if that page is present further translation is made, this means that Hardware (TLB is a hardware) returns frame no. of the frame where the page is present. Translation means whatever is done by hardware after it checks Valid bit = 1. (because page hit can be said only after seeing $valid = 1$

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Yes :)  it is correct and conclusion is inside TLB  if normal hit then only one adress translation (VA->PA)occur and that is done by TLB H/W(Associative memory). And after that there no any further translation is required and we can get directly our PA content(memory word).

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Well, that's what i meant from translation.

Answer 1

Lot of discussion on it. So, trying to summarize:

TLB entry present - we have a valid address translation - so page address is valid (page frame is present in main memory).

Can we still get page fault - yes, if the memory address is illegal access, we can get page fault as when we try to write to a Read Only page.

Comments

Correct Sir

Thanks a lot @mcjoshi for healthy discussion.

Hope we drink a tea 2gether on a fine evening :p

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Yes(one evening), but i will love to host.
you decide venue.

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@Arjun, its the valid bit that will decide if the page is present in memory or not, right? Why dirty bit then?

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once TLB hit occurs we can tell valid translation exist means we have corresponding frame no. in main memory for the page no. which TLB entry is found

but accessing that frame from MM can lead to page pault , to check we will see page table entry information of the page table:

->we are trying to write and it is read only page

->page is dirty(modified in last clock cycle)

->valid bit is reset in page table (page which we are trying to access is invalid)

so Illegal access can lead to page fault even if translation is valid(we have frame no. for the page we are looking for)

Answer 2

TLB is a cache specially designed for page table mappings. Each entry in the TLB has the two basic fields: a tag field , a data field which is the size of the physical page number (pointer to that location), and several bits that indicate the status of the TLB line or of the page associated with it. These bits usually are a dirty bit which indicates if the corresponding page has been written, a reference bit which indicates if the corresponding page has been accessed, and a write protection bit which indicates if writes are allowed in the corresponding page.

At every memory reference the TLB is accessed with the virtual page number field of the virtual address. If there is a hit (hit can be said only by looking $\color{green}{valid-bit = 1}$), then, TLB (Hardware) returns frame no. of the frame where the page is present If there is a miss in the TLB (this is also called translation), the control must determine if there is a real page fault or a simple TLB miss.

TLB miss can be quickly resolved by updating the TLB entry with the proper information from the page table residing in main memory. In the case of a page fault the CPU gets interrupted, and the interrupt handler will take the necessary steps to service the fault.

PS:) Page fault refers to the scenario where the obtained translation cannot be effectively used. It may be a missing page or a dirty page or access permission mismatch. So, a TLB hit can still lead to a page fault.

Comments

@mcjoshi Share ur Reference of ur source of TLB.
#Edit
protection bits determine how a page can
be accessed (as in the page table). For example, code pages might be marked read and execute, whereas heap pages might be marked read write.

https://www.google.co.in/url?q=http://pages.cs.wisc.edu/~remzi/OSTEP/vm-tlbs.pdf&sa=U&ved=0ahUKEwib_YzkmdrPAhVBRY8KHY3MClsQFggkMAc&usg=AFQjCNEsBLwdWTQ7hap-Z9RmUdd6Gu-0uw

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Dirty bit means whether the page has been written in last clock cycle (or) not.

Source : Read this

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Yes Dirty bit of TLB is similar to Page table.

Imp note:-And One more imp thing In a protected memory system, a context switch implies the use of a new page table. Clearly then, the old page table must have the dirty and reference bits synchronised with the TLB, which must then be flushed of all entries. The TLB must then be slowly filled as pages are accessed, according to the specified operations. This can be a fairly expensive operation, and when rapid context switching occurs it can severely impact performance.