in Digital Logic edited by
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A sequential circuit takes an input stream of $0's$ and $1's$ and produces an output stream of $0's$ and $1's.$ Initially it replicates the input on its output until two consecutive $0's$ are encountered on the input. From then onward, it produces an output stream, which is the bit-wise complement of input stream until it encounters two consecutive 1's, whereupon the process repeats. An example input and output stream is shown below.

$\begin{array}{ll}
\text{The input stream:} &  101100|01001011|011\\
\text{The desired output:}&  101100|10110100|011\\
\end{array}$

$\text{J-K}$ master-slave flip-flops are to be used to design the circuit.

  1. Give the state transition diagram
  2. Give the minimized sum-of-product expression for $\text{J}$ and $\text{K}$ inputs of one of its state flip-flops
in Digital Logic edited by
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2 Comments

Guys, it would be helpful if you please explain this more clearly.
0
Beautiful question to clear our concepts.
0

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2 Answers

30 votes
 
Best answer

We can design a Mealy Machine as per the requirement given in the question. 

From which we will get state table, and we can design sequential circuit using any Flip-flop from the state table (with the help of excitation table) :

As we get $4$ states (renaming state component to binary states), we need two FFs to implement it.

Let $A$ and $B$ be present states, $x$ be the input and $y$ be the output.$$\small \begin{array}{c|c|c|c|cc|cc|}
\text{Present State}&\text{Input}&\text{Next State}&\text{Output}&\rlap{\text{FF}}&&\rlap{\text{FF}}\\
&&&&\rlap{\text{inputs}}&&\rlap{\text{inputs}}\\
\hline
AB&X&A'B'&Y&J_A&K_A&J_B&K_B\\\hline
00&0&01&0&0&X&1&X\\
00&1&00&1&0&X&0&X\\
01&0&10&0&1&X&X&1\\
01&1&00&1&0&X&X&1\\
10&0&10&1&X&0&0&X\\
10&1&11&0&X&0&1&X\\
11&0&10&1&X&0&X&1\\
11&1&00&0&X&1&X&1\\
\end{array}$$ \begin{array}{cc|cc} Q_t&Q_{t+1}&J&K\\\hline 0&0&0&X\\0&1&1&X\\1&0&X&1\\1&1&X&0\end{array}

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16 Comments

In the question they mention " J-K master-slave flip-flops are to be used to design the circuit. "

But you did with Melay and Moore
0
@shaik .. it is state machine to sequential logic circuit
2
nice idea praveen sir
0
Sir how to draw this mealy machine
0
as you did in TOC.
0
Sir how the solution will change if we had to do it using norml JK Flip Flop
0
you can refer my answer, for normal J-K flipflop

But with master slave J-K flipflop i don't know.

Moreover no need to call me as sir, you can call me with my name
0

  Can u please write your solution in detailed manner like this answer.

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there is no need of it, For avoiding confusion, i removed my answer !
0

  Please add your answer. I want to learn to design circuit without Master Slave Filp Flop also

0
Actually i made the wrong statement, sorry for that !

there is no specific representation for Master-slave FF, in this answer the A flipflop and B flipflops are Master slave Flipflop's only ! ( the internal circuit is different for normal and master-slave, but o/p is same. )

Then Why my answer is not Matching ?

without state diagram, i tried and got with 3-FF, it is not minimized !
1

Just one doubt how could you replace q0 with 00.. why can't we replace it with 11(or any other combination).. can you please help me with this @Shaik Masthan @Praveen Saini

1
normally in the state diagram, the states are represented the o/p of FF's only.

By taking the initial state as 00, we form that entire sequence !
0

normally in the state diagram, the states are represented the o/p of FF's only.

Here what is the output of FF, we don't know about it right ??

 By taking the initial state as 00, we form that entire sequence !

I agree we generally take 00 as initial state unless it is specified to take any other value, but how will the second state be 01 ? :(

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@sambhrant using excitation table of FF, where present state and next state is given.
0

@Shaik Masthan Sir

the master slave JK flipflop are a modification of  normal JK flipflop to avoid RACE AROUND condition in JK Flipflop when we use level trigerred flipflops.

If we use edge trigerred then no use of master slave JK  flipflop.right?

0
31 votes

As we get $4$ states (renaming state component to binary states), we need two FFs to implement it.

edited by

8 Comments

Why to use 2 FF.?
1
we need to deal with 4 states.
4 states need 2 bits to represent them. Hence 2 Flipflops.
4
@praveen sir , how transations are going on can u explain bit more? ... m getting how op is comming
1
look at problem as two parts, first we are looking at 00, till 00 each output is same as input, 0/0,1/0. once we get 00 then we are looking for 11, till 11 each output is complement of input, 0/1, 1/0.
1

@Praveen+Saini

Sir,

It looks similer to FA concept in TOC :)

Why can't we use NFA here.it would have cost 3 states ..

0
nice thinking praveen sir
0
NFAs are not used in practical applications because they are non deterministic ( you will not be sure about the output).
0
On getting 0 at q0 why do we go to q1? I really don’t understand what does the state names depict.
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