Stall Cycles-Without Forwarding

Question

anyone elaborate the reason for each stall cycles.

Comments

In the absence of operand forwarding, the subsequent instruction which require data value which is being modified by the preceeding instruction, has to wait all the way until the modification has been performed. As you can observe the second instruction stalls for stages EX and M because a correct value of the operand is not available, however once both the stages have been traversed by the preeceding instruction, the current instruction can enter the ID stage with consistent value of the operand

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on 9th cycle why IF is done for the last instruction

Answer 1

Instruction

1

2

3

4

5

6

7

8

9

10

11

12

13

14

lw $1, 40($6)

IF

ID

EX

M

WB

add $2,$3,$1

IF

_

_

ID

EX

M

WB

add $1,$2,$6

IF

_

_

ID

EX

M

WB

sw $2,20($ 4)

IF

ID

EX

M

WB

and $1,$1,$4

IF

_

ID

EX

M

WB

In this question, there is no forwarding technique used.

So, here we can only use split phase.

• In 1st instruction, that is a LOAD instruction. So, we get value of instruction at last of MEM stage.
• 2nd instruction depend on 1st instruction.So, decode (reading) phase of 2nd instruction starts after MEM stage of 1st instruction.
• 3rd instruction depend on 1st and 2nd instruction. 3rd instruction is simply another ADD instruction .So, writing of 2nd can do in same cycle of reading of 3rd instruction, where writing done 1st half of cycle and reading in last half of cycle.
• 4th instruction depend on 2nd instruction. So, no stall require here.
• 5th instruction depend on 3rd instruction. So, writing of 3rd can do in same cycle of reading of 5th instruction, where writing done 1st half of cycle and reading in last half of cycle.So, one stall in this instruction too.

 

So, total these 14 cycles are present

Comments

please check my answer once.

There is a Write-Read dependency between $I_{5},I_{3}$ between WB-ID stage

• 5th instruction depend on 3rd instruction. So, writing of 3rd can do in same cycle of reading of 5th instruction, where writing done 1st half of cycle and reading in last half of cycle.So, one stall in this instruction too.

isnot it? 

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Yes there is dependency between i3 and i5.

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@Shaik Masthan

So, answer 14, right??

And what about CPI of $I_{2}?3??$

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(We can calculate CPI in cache memory and also CPI is in pipeline, uff !! CPI causing my confusion.)