Main memory access time= $100*10^{-9}$
Clock cycles=$\frac{1}{clock rate} = \frac{1}{5*10^9}$
Miss penalty without L2 cache =$\frac{100*10^{-9}}{\frac{1}{5*10^9}}$=500 clock cycles
L2 cache access time= $5*10^{-9}$
Miss penalty with L2 cache =$\frac{5*10^{-9}}{\frac{1}{5*10^9}}$=25 clock cycles
Therefore, miss penalty reduced by 475 clock cycles.