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Consider a system with CPI of 1.0 on a 5 GHz machine with a 2% miss rate and memory access time of 100ns. To reduce miss penalty designers decided to add a L2 cache with 5ns access time and decrease of overall main memory miss rate to 0.5%, How many clock cycles miss penalty reduced?
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Main memory access time= $100*10^{-9}$

Clock cycles=$\frac{1}{clock rate} = \frac{1}{5*10^9}$

Miss penalty without L2 cache =$\frac{100*10^{-9}}{\frac{1}{5*10^9}}$=500 clock cycles

L2 cache access time= $5*10^{-9}$

Miss penalty with L2 cache =$\frac{5*10^{-9}}{\frac{1}{5*10^9}}$=25 clock cycles

Therefore, miss penalty reduced by 475 clock cycles.

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