# Digital Logic

1 vote
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The 4 bit shift register is initialized to value 1000 for (Q3,Q2,Q1,Q0) . The D input is derived from the Q0,Q2,and Q3 through two XOR gates as shown in figure below . The Pattern 0001 will appear at pulse ------------------- ?

D   Q0  Q1 Q2 Q3   and logic gates are XNOR (order in image . I wrote it because in the image it is              not clear) .

retagged

0001 will appear after 6 clock pulse...
0001
1000
1100
1110
0111
0011
0001

edited
1
But question is about 1000 pattern . fine ! 0001 will get printed at 6th clock cycle. so 1000 will get printed at 7 clock cycle
0
question clearly says 0001 pattern nd 0001 corresponds to q0q1q2q3... at starting of the question 1000 is given as (q3q2q1q0) that's why I reversed it to q0q1q2q3...
so at starting 0001 is present
so when will give  first clock pulse it is  1000
at 2nd clock pulse1100
similarly at 6th clock pulse it will be 0001 pattern corresponding to diagram (q0q1q2q3)...
1
At the last pattern 0001 desired . As in the question initially pattern was 1000 (q3,q2,q1,q0) so you reversed it for q0,q1,q2,q3 .

Same thing should be considered for desired pattern also ? As 0001 given means (q3,q2,q1,q0) .. so that means desired pattern at the last 1000 (q0,q1,q2,q3)??.

As they gave first pattern which is q3,....q0 order so desired pattern is also in this order only.

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