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The 4 bit shift register is initialized to value 1000 for (Q3,Q2,Q1,Q0) . The D input is derived from the Q0,Q2,and Q3 through two XOR gates as shown in figure below . The Pattern 0001 will appear at pulse ------------------- ?

             D   Q0  Q1 Q2 Q3   and logic gates are XNOR (order in image . I wrote it because in the image it is              not clear) .

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0001 will appear after 6 clock pulse...
0001
1000
1100
1110
0111
0011
0001
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