Assume we have a computer where the cycles per instruction (CPI) is 1.0 when all memory accesses hit in the cache.The only data accesses are loads and stores, and these total 50% of the instructions. If the miss penalty is 25 clock cycles and the miss rate is 2%, how much faster would the computer be if all instructions were cache hits?
- 1.5
- 0.7
- 2.75
- 1.75