size of cache

Question

A 2-way set associative write back cache with true LRU replacement requires 15 * 2⁹ bits to implement its tag store per set (including bits for valid, dirty and LRU). The cache is virtually indexed, physically tagged. The virtual address space is 1 MB, page size is 2 KB, cache block size is 8 bytes and is byte-addressable.
What is the maximum size of the data store of the cache in bytes?

1.   9 KB
2.   10 KB
3.   12 KB
4.   8 KB

Answer 1

 

Here after TLB we will get physical addres with that physical address we need to check tag. Index directly go throught cache.Thats why it is called virtually indexed physically tagged. Advantage of this type of oarchitecture is that no flushing is requirred.It gives advantages of both arcyhittecture physically indexed and virtually index cache.

Now , for the given question ...

lets take 2^k sets are available since k is the index bits , for each set we need 2 valid,2 dirty and 1LRU bits ( 1 bit is sufficint for LRU).

SO 2^K (2++2+1 + (2*tag bits)) = 15* 2⁹ here data is given such that u can directly find the value of tag bits here one point needs to be note down since cache is physically tagged so we can not find tag using virtual address space.

2^k (5 + 2*tag) =2⁹ * 15    

So 15 = 5+2*tag   so tag=5

so 2⁹ ((5*2 + 5 (valid+dirty +LRU)) ) = 2⁹ * 15 = approx 2¹³B = 8KB

                                 

Comments

t is tag bit

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when u r taking line u have to use single tag bits , 1 protection and 1 dirty and so on...but LRU bit for set ...1 set having 2 block so 1 bit is sufficient...but question is framed such a that by taking lines u can not get ans...

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@Arjun sir 

flushing means when context switch has been happen we need to flush or invalidate cache so that same virtual address will not going to map with previous processs addresses and data..

this problem happen incase of virtually indexed virtually tagged cache...as tag checking done using virtual address ...

but incase of vitually indexed physicaly tagged , tag bits are mappped using physical address and "Two process can not have same physical address" even indexed has been matched but tag doesn't map. so no flushing required.

But aliasing problem can not be removed fully ...as long as cache size is small enough no aliasing problem will arrive...This is one of advantage ove VIVT cahce...