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+55 votes
The minimum number of JK flip-flops required to construct a synchronous counter with the count sequence (0, 0, 1, 1, 2, 2, 3, 3, 0, 0, ...) is _______.
in Digital Logic by Veteran (105k points)
edited by | 14.2k views
$(0_{1}, 0_{2}, ...)$

If we use only 2 - F/F then we can not predict machine is on $0_{1}$ or  $0_{2}$ .So one more F/F is required.
i think 3. first flip flop will help in delaying the next input so that output can be same for 2 clock cycles
But the answer given in book is 2 and I don't understand the answer.

you are not able to understand the solution on this website too? 

Not fully. I have a doubt that if I take 0,1,0,2,0,3,0,1,0,2,0,3,......then

okay, can you wait for sometime? i'll add precise explanation to that question

also this lecture have an excellent explanation how counters work.

Yaa sure

And one think I want to ask that in give solution why they should add one more bit at MSB and why they should follow specific pattern of bit i.e. 0 1 0 1 0 1 0 1 0 at MSB.
I have basic doubt here

what is sequence here ?

is it

0, 0, 1, 1, 2, 2, 3, 3, 0, 0 (in this case 4 FF needed )


0, 0, 1, 1, 2, 2, 3, 3 (in this case three FF needed)

@mehul vaidya same doubt occuring here,

9 Answers

+129 votes
Best answer
First, lets design a counter for $0, 1, 2, 3$. It is a MOD - $4$ counter. Hence, number of Flip Flops required will be two. Count sequence will be:

$00 \to 01 \to 10 \to 11$
Count sequence mentioned in question is:

$00 \to 00 \to 01 \to 01 \to 10 \to 10 \to 11 \to 11$
Now, two flip flops won't suffice. Since we are confronted with repeated sequence, we may add another bit to the above sequence:

$000 \to 100 \to 001 \to 101 \to 010 \to 110 \to 011 \to 111$
Now each and every count is unique, occurring only once. Meanwhile, our machine has been extended to a MOD - $8$ counter. Hence, three Flip Flops suffice.

Just neglect the MSB flip flop output and take the o/p of other two only. So, we have :

by Active (5.2k points)
edited by
is nt it 4 by above logic ?

To generate the sequence 0,1,2,3,4,5,6,7 we require log2(8)= 3 JK flip flops.

doesnt synchronous counter take help of additional AND gates to generate mod 8 counter with 3 flipflops? 

That's what I said.

"Ignore first bit" means don't consider it for sequence. It doesn't mean to ignore a flip flop.
Where is the restriction saying "no other gates can be used". To realize a counter we can surely use any gate if not restricted.

yeah i agree with all that, i have nly this doubt
forget abt the sequence given in ques.
how many flipflops are needed to generate mod8 synchronus counter?
@srestha i m agree with u for actual problem i think 2 was right ans but in official key it is 3 then what should we do.....
even 1 prof of iitm explains the above problem with 2ff nd 1 external i/p to distinguish between states.

For ring counter it is 8.

For jhonson counter it is 4.

Best case: gray counter or some random counter, it is log2(8) = 3.

It think it should be enough.

@saurabh i did not think answer for this is 2.
@rajendra i thought we shudnt use any additional logic gates
no i mean 2 is for actual problem
nd 3 is for ur problem iff extra h/w allowed
obviously 3
"even 1 prof of iitm explains the above problem with 2ff nd 1 external i/p to distinguish between states."

please explain how??


Perhaps you didn't listen the lecture fully well. He said an external input maybe used but then again in the case of counters you can't do that, so that you have to stick to 3 FFs only.

You can watch that video again after 30 min dureation approx.


You can discard the MSB bit that is completely fine, but the question mentions the word sequence, and the word sequence means -> something which should always happen in the specified order.

But your technique of discarding the MSB of mod 8 counter fails to maintain the sequence:

it will generate terms as below:









which is not the sequence which they asked for, ckt below although requires 5 JK FF but seems to solve this problem considering the initial state of Q1 and Q0 as 0 , 0 and all 5 FF sharing same clock, is it possible to file RTI to Gate authorities to retrieve their way of solution







$3$ is the right answer and verified.
I saw that on GATE key present in the link above, but dubious about the approach.
No, $3$ is the final answer.

I know its most confusing answer but finally, $3$ is the right answer.

You can get this by $2-3$ approaches, though the best one is first to take $2$ bits for representing $4$ numbers and then append $0\;\text{or}\;1$ to distinguish between the same values.
Yaa... I know the final answer is 3 but you please help me in understanding why this approach is not producing the answer with the proper sequence as mentioned in the Question.

or please share with me the approach (among 2-3) which produces a result with the correct sequence.

Thanks in Advance !!!
When you said "It is a MOD - 4 counter. Hence, number of Flip Flops required will be two." To find number of flip flops required, are you taking log4=2 or 4/2=2. I am asking this because i think in synchronous counter , maximum number of counting states can be 2N, where N is number of flip flops. Here in question, synchronous counter is mentioned.So number of flip flops=4/2=2. Whereas in asynchronous, max counting states can be 2^N. Am I correct?


Synchronous counter without combinational circuit can count 2N states.

but with combinational circuit can count upto 2^N state.

Check it out.....below circuit works for the above question.

+22 votes
People are asking for explaination , I am not giving full solution but an approach how to handle these kind of questions .

First for creating  counter for any sequence we need to identify the states .

Lets say we are taking a sequence of 0-1-2-3 then the states of flip flop (counter design) will be (ff1-ff0) 00->01->10->11-> , only 2 flipflop will be sufficient to give output in 2 bits.

but for the above sequence as you see there are two digits of same kind  0,0,1,1,2,2,3,3 , for which binary values will be 00,00,01,01,10,10,11,11 we cant diffrenciate first 00 from 2nd 00 or third 01 from fourth 01 using only 2 bits so we will add 3rd bit as follow

000,100,001,101,010,110,011,111 here if you see i have just added one extra bit and we can now differenciate between each number seperately , if we made a counter for this sequence and take output of only  first two flipflops (ff1,ff0) from (ff2,ff1,ff0) then our sequence is realized.


(PS for futher clearance on the topic refer Morris Mano book )
by (103 points)
+8 votes

Here it appears to have 8 discrete states. That requires 3 bits, therefore 3 flip-flops. From inspection, there are 4 groups of 2 identical bits per group. I'd break that down to into a divide by two (1 flip-flop) followed by a divide by four (2 flip-flops).

by Boss (13.6k points)
Explain plz??
pls explain.!!!!!!!!

...getting confused by your answer.
how to realize the circuit. for this problem
If $A,B, C$ are the bits of present input and $A^+,B^+,C^+$ are the bits of next output, the steering logic in the counter design will be :



+4 votes
question is slightly ambigus.the thing is we can get sequence 0,0,1,1,2,2,3,3, by 2 FF.


the o/p of the FF will be sampled at twice the i/p clock frequency.

e.g. let my FF retains a state for 2 seconds and i sample o/p at 1 second interval.

and this is quite possible.

and other cases users have already discussed
by Active (2.3k points)
But that way, it will be an asynchronous counter.
+2 votes
The patter can be generated by a mod 8 counter so the answer is 3.
by Active (1.4k points)
how?? plz explain
Pls explain it...
+2 votes
only 3 flip flop needed
by Active (5k points)
+2 votes

Found something interesting. Guys at MadeEasy were able to do this with 2 flip flops using an additional clock.

Although I would like to clarify that the answer in the official sheet is 3.

 MadeEasy answer

by Active (2.2k points)
that's why writers on GATE OVERFLOW are much better than made easy/ace/any other coaching institute's writers.
This is not a classic example of a synchronous counter. Although we could do that but it will become advance level.
0 votes
2 should be correct because using some extra gates along with Flip-Flops we can count this sequence.
by (35 points)
Can you kindly elaborate what kind of ckt can be used along with flip-flops to obtain above sequence ? As per my understanding, a frequency divider ckt (divide by 2) can be used, but then it will require one more flipflop along with two output flipflops. Hence 3 flipflops in total. Is there any other method which uses less than 3 flipflops?
I think as GATE AUTHORITY mentioned the counter as synchronous counter then we can go for the Clock frequency sampling policy(changing its period length).. By this we can accomplish the task with 2 flip flop... BUT MAY BE ITS WRONG.

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