@Divyanshu Shukla Assuming the CPU is in IDLE state and then suddenly there is an interrupt due to some sensor and DMA is requesting a bus for printer operation simultaneously. We have to see whether the HOLD signal is high or low during the CLK=1, if it is high, then the DMA request will be prioritized, and if it is low, then such interrupt(generally non-maskable in modern systems) will be prioritized.
@VIDYADHAR SHELKE 1, @jiminpark, @Pranavpurkar, If the internal interrupt is maskable(which is a rare scenario in modern systems), then it will not be given more priority w.r.t. DMA request. But if the internal interrupt is non-maskable, which is the general scenario in modern systems, an interrupt like a temperature sensor “may” trap the CPU. And we have to see the strength of the HOLD signal in the next Clock.
HOLD vs. Interrupts scenario -
In the case of 8085A, it uses the T(hold) state to momentarily cease executing machine cycles, allowing external devices to gain control of the bus and perform DMA cycles.
As regards T(hold) and T(halt), three situations can occur: ( During T(halt) – the CPU stops executing the instructions and is IDLE.)
1- The CPU is in T(halt) state – During CLK=1 of every T(halt) state, the processor internally latches: (a) the state of the HOLD line, (b) Any unmasked interrupts. If the HOLD is high, then on the following CLK=1 CPU exits T(halt) and enters T(hold). This takes place even if a valid interrupt co-occurs with the HOLD signal(which is high).
2- The CPU is in T(hold) state: During CLK=1 of every T(hold) state, the processor internally latches: (a) the state of the HOLD line, (b) Any unmasked interrupts. If the HOLD is low, then on the following CLK=1 CPU exits T(hold) and enters T(halt). If any unmasked interrupt is present, the CPU accepts only the first unmasked enabled interrupt: after that, all other interrupts are ignored regardless of their intrinsic priorities.
3- When the CPU is not in T(halt) or T(hold):
- It internally latches the HOLD line only during CLK = 1 of the last state before T3(T 2 or T WAIT) and during CLK = ·1 of the previous state before T5 (T4 of a six T-state M1). If the internal latched HOLD signal is high during the next CLK = 1, the CPU will enter T(hold) after the following clock
- It will internally latch the state of the Unmasked interrupts only during CLK of the next to the last state before each M1 • T1.
Ref. – (1)http://www.bitsavers.org/components/intel/MCS80/MCS80_85_Users_Manual_Jan83.pdf (Page no. 40)
(2) Microprocessor System, Page Number 28