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+37 votes

For computer based on three-address instruction formats, each address field can be used to specify which of the following:

(S1) A memory operand

(S2) A processor register

(S3) An implied accumulator register

  1. Either $S1$ or $S2$
  2. Either $S2$ or $S3$
  3. Only $S2$ and $S3$
  4. All of $S1$, $S2$ and $S3$
in Compiler Design by Boss (30.8k points)
edited by | 4.9k views
According to me, it should be D) Arjun sir, what is the correct answer?
Question is asking for 3 address instruction format and not 3 address codes. In an instruction, an address filed can refer to a memory or register. Implied registers are not mentioned in any instruction. The usage of "three instruction" in question is just to create confusion.
@Arjun sir
Means we can only reference register or memory with single address field or with all 3 address fields.
If there is 3 address code in question in place of 3 address instruction, then what will be answer ?? how 3 address codes are stored ??
what is implied Accumulator register??
implied addressing modes have one of the operand (destination i.e the accumalator ) as fixed hence we always use only one address in the instruction which may be a memory address or a register like LOAD X   or  LOAD R1  this will load the contents of the memory locations or the registers to the implied operand which is the accumulator we need not specify the accumulator explicitly in the instruction

Implied Accumulator is used in Single Accumulator Organization:


For those asking "what if 3-address code instead", from Wikipedia -:

"Since three-address code is used as an intermediate language within compilers, the operands will most likely not be concrete memory addresses or processor registers, but rather symbolic addresses that will be translated into actual addresses during register allocation."

3 Answers

+44 votes
Best answer

Three address Instruction

Computer with three addresses instruction format can use each address field to specify either processor register or memory operand.

e.g., $X = (A + B) * (C + A)$

Equivalent Three address Instructions$$\begin{array}{ll}
\text{ADD } R1, A, B &    ;\qquad R1 \leftarrow  M [A] + M [B]\\
\text{ADD }R2, C, D & ;\qquad R2 \leftarrow  M [C] + M [D]\\
\text{MUL } X, R1, R2    & ;\qquad M [X] \leftarrow  R1 * R2
\end{array}$$The advantage of the three address formats is that it results in short program when evaluating arithmetic expression. The disadvantage is that the binary-coded instructions require too many bits to specify three addresses.

Correct Answer: $A$

by Active (4.7k points)
edited by
what is answer ?

@Rishabh Gupta 2 why not accumulator though all the operations are performed in accumulator?

also  one of the operand always need to be present in accumulator.

Given link doesn't work anymore.

Implied Accumulator is used in Single Accumulator Organization:

According to Carl Hamacher, it is given that, Instructions in modern CISC processors typically do not use a three-address format. Most ALU instructions use the two-address format.

That means RISC only use 3-address format and for RISC, the operations can only be performed in registers and not directly from the memory. Then how S1 can be true? Please explain.

@Aarvi Chawla read Arjun sir's comment in the comment section of question 
it will be clear

+22 votes

option A either A memory operand or  A processor register.

by Active (5k points)
no it should be option c
in place of 3 address instruction if it is 3 address code then ans will D??
+1 vote

Option A: (in inst' n never present accumulator register address)

by (83 points)

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