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A device employing INTR line for device interrupt puts the CALL instruction on the data bus while:

  1. $\overline{INTA}$ is active
  2. HOLD is active
  3. READY is inactive
  4. None of the above
asked in CO & Architecture by Veteran (59.7k points)
edited by | 1.8k views
0
is it in syllabus ??

4 Answers

+15 votes
Best answer

INTR is a signal which if enabled then microprocessor has interrupt enabled it receives high INR signal & activates INTA signal, so another request can’t be accepted till CPU is busy in servicing interrupt. Hence (A) is correct option.

answered by Junior (697 points)
edited by
+8
This is a CO question or a microprocessor question?
0
The processor enables INTA signal but in question (INTA)' is given{notice that compliment sign on INTA}.
Then also option A will be true?

I think then Option D should be correct.
+2
No, it is INTA' instruction, it means Interrupt Acknowledge, option A is correct here.
+1
Yes, INTR, INTA'  this are Microprocessor signals  ( 8085) .

This is related to machine instructions part in COA.
0
what relation does call instruction have with interrupt?
+12 votes

A device employing INTR line for device interrupt puts the CALL instruction on the data bus

This line means when a interrupt request signal( INTR )  is enabled then microprocessor has to enable that interrupt  .

It receives high INTR signal and activates INTA' signal, So another request can’t be accepted ( put on CALL )  till CPU is busy in servicing interrupt . 

INTR is an interrupt request signal it's full form is Interrupt Request .

 It has the lowest priority among the interrupts. INTR can be enabled or disabled by using software. Whenever INTR goes high the microprocessor completes the current instruction which is being executed and then acknowledges the INTR signal and processes it.

The INTA' signal means interrupt acknowledge signal .

 Once an instruction is completed the processor sends an acknowledgement signal INTA'. ( which mean i have acknowledged your interrupt , wait till i will  provide you a service )

Whenever the microprocessor receives interrupt signal. It has to be acknowledged. This acknowledgement is done by INTA’.

So whenever the interrupt is received,  INTA’  goes high.

 Once the new instruction is received the processor saves the address of new instruction into the STACK and an interrupt service subroutine begins.

CALL instruction saves procedure linking information on the stack and branches to the procedure (called procedure) specified with the destination (target) operand .

All that means Option A is correct here .

answered by Veteran (71.5k points)
0
+9 votes
In a daisy chaining method , all the device are connected to a single INTr and INTA line .

No if anyone device has generated Interrupt or more than one they will raise INT signal .

But the CPU will repond to it after servicing the current instruction .

after that , it will  do polling from higher priority device to lower priority device ( not a fair sharing system ) to find out which device has generated inteerupt .

now as soon as it find the device it will enable INTA signal -- which mean i have acknowledged you , wait i iwll service you !

Now as soon as INTA is recived by interuupting device, it will pass it vector address ( CALL XXXX H ) so that CPU can service it with its ISR .

is this the correct  reaosn behind  this question @arjun sir ?
answered by Loyal (10k points)
+2 votes

Some signals to be remembered:
 

IO/M’:

Consider we have an address to be processed. But how do the processors know whether the address is for memory or I/O functions? For this purpose a status signal called IO/M’ is used. This distinguishes whether the address is for memory or IO. When this pin goes high, the address is for an I/O device. While the pin goes low, the address is assigned for the memory.

RD’:

This is an active low signal. That is, an operation is performed when the signal goes low. This signal is used to control READ operation of the microprocessor. When this pin goes low the microprocessor reads the data from memory or I/O device.

WR’:

WR’ is also an active low signal which controls the write operations of the microprocessor. When this pin goes low, the data is written to the memory or I/O device.

READY:

READY is used by the microprocessor to check whether a peripheral is ready to accept or transfer data. A peripheral may be a LCD display or analog to digital converter or any other. These peripherals are connected to microprocessor using the READY pin. If READY is high then the periphery is ready for data transfer. If not the microprocessor waits until READY goes high.

HOLD:

This indicates if any other device is requesting the use of address and data bus. Consider two peripheral devices. One is the LCD and the other Analog to Digital converter. Suppose if analog to digital converter is using the address and data bus and if LCD requests the use of address and data bus by giving HOLD signal, then the microprocessor transfers the control to the LCD as soon as the current cycle is over. After the LCD process is over, the control is transferred back to analog and digital converter.

HLDA:

HLDA is the acknowledgment signal for HOLD. It indicates whether the HOLD signal is received or not. After the execution of HOLD request, HLDA goes low.

INTR:

INTR is an interrupt request signal. It has the lowest priority among the interrupts. INTR can be enabled or disabled by using software. Whenever INTR goes high the microprocessor completes the current instruction which is being executed and then acknowledges the INTR signal and processes it.

INTA’:

Whenever the microprocessor receives interrupt signal. It has to be acknowledged. This acknowledgement is done by INTA’. So whenever the interrupt is received INTA’ goes high.

 

answered by Active (1.2k points)
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