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A device employing INTR line for device interrupt puts the CALL instruction on the data bus while:

1. $\overline{INTA}$ is active
2. HOLD is active
4. None of the above
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INTR is a signal which if enabled then microprocessor has interrupt enabled it receives high INR signal & activates INTA signal, so another request can’t be accepted till CPU is busy in servicing interrupt. Hence (A) is correct option.
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This is a CO question or a microprocessor question?
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The processor enables INTA signal but in question (INTA)' is given{notice that compliment sign on INTA}.
Then also option A will be true?

I think then Option D should be correct.
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No, it is INTA' instruction, it means Interrupt Acknowledge, option A is correct here.
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Yes, INTR, INTA'  this are Microprocessor signals  ( 8085) .

This is related to machine instructions part in COA.

A device employing INTR line for device interrupt puts the CALL instruction on the data bus

This line means when a interrupt request signal( INTR )  is enabled then microprocessor has to enable that interrupt  .

It receives high INTR signal and activates INTA' signal, So another request can’t be accepted ( put on CALL )  till CPU is busy in servicing interrupt .

INTR is an interrupt request signal it's full form is Interrupt Request .

It has the lowest priority among the interrupts. INTR can be enabled or disabled by using software. Whenever INTR goes high the microprocessor completes the current instruction which is being executed and then acknowledges the INTR signal and processes it.

The INTA' signal means interrupt acknowledge signal .

Once an instruction is completed the processor sends an acknowledgement signal INTA'. ( which mean i have acknowledged your interrupt , wait till i will  provide you a service )

Whenever the microprocessor receives interrupt signal. It has to be acknowledged. This acknowledgement is done by INTA’.

So whenever the interrupt is received,  INTA’  goes high.

Once the new instruction is received the processor saves the address of new instruction into the STACK and an interrupt service subroutine begins.

CALL instruction saves procedure linking information on the stack and branches to the procedure (called procedure) specified with the destination (target) operand .

All that means Option A is correct here .

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In a daisy chaining method , all the device are connected to a single INTr and INTA line .

No if anyone device has generated Interrupt or more than one they will raise INT signal .

But the CPU will repond to it after servicing the current instruction .

after that , it will  do polling from higher priority device to lower priority device ( not a fair sharing system ) to find out which device has generated inteerupt .

now as soon as it find the device it will enable INTA signal -- which mean i have acknowledged you , wait i iwll service you !

Now as soon as INTA is recived by interuupting device, it will pass it vector address ( CALL XXXX H ) so that CPU can service it with its ISR .

is this the correct  reaosn behind  this question @arjun sir ?