MadeEasy Test Series: CO & Architecture - Pipelining

Question

Answer 1

Where time = max(stage delays) + buffer delay.

P1  is 4 stage pipeline and only 3 stage delays are given . ( data insufficient ) But with given data time is 2+0.5 = 2.05 ns
P2  time = 1ns + 1ns = 2ns
P3  time = 2ns + 0ns = 2ns
P4 time =  1ns + 0.5ns = 1.5 ns

Frequency = 1 /time

P2 and P3 having same frequency .

Highest Frequency is for less time delay.
P4 is the answer

Comments

P4 has less time..so it would have more frequency..is not it?

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Yes . corrected . I do commit silly mistakes all the time :(

Answer 2

Frequency = 1 /time

Where time = max(stage delays) + buffer delay.

For P1 one stage delay is missing .

For P2 = 1 / 2 = 0.5 

For P3 = 1 / 2 = 0.5

For P4 = 1 / 1.5 = 0.67 

So P4 is ans.

Comments

I think you didnt add buffer delays .

Answer 3

Frequency of the pipeline is the reciprocal of the time in which information is transferred from one stage to another. So frequency is independent of number of stages.

P1 : t =  2.5 (data insufficient)

P2  : t = 2

P3 : t = 2

P4 : t = 1.5

So P4 has least time period. Therefore it has maximum clock frequency with which it's pipeline operates.