The designer of the processor claims that it will have an average memory latency of 1.5 cycles. The design includes a 1 cycle access to the L1 cache, an additional 6 cycles to the L2 cache, and 120 cycles to main memory. The designer has made assumptions about the hit ratios of the L1 and L2 caches. (a) If she assumed the L2 cache never misses, what has she assumed about the L1 cache hit ratio?Plz explain
