4 votes 4 votes Digital Logic digital-logic k-map combinational-circuit + – Rakesh K asked Nov 14, 2016 Rakesh K 8.6k views answer comment Share Follow See all 0 reply Please log in or register to add a comment.
Best answer 8 votes 8 votes Here we are getting output as Y'=A'BC+AB'C+ABC'+ABC =AB+BC+AC =((A(B'C')')' (BC)')' So, total 6 NAND gates are required. If complemented and uncomplemented variable both present then minimum NAND gates are 4 srestha answered Nov 14, 2016 selected Dec 15, 2017 by LeenSharma srestha comment Share Follow See all 4 Comments See all 4 4 Comments reply Rakesh K commented Nov 14, 2016 reply Follow Share Is there any method to reduce AB+BC+AC to ((A(B'C')')' (BC)')' ? 0 votes 0 votes srestha commented Nov 14, 2016 reply Follow Share No, just put demorgan law (A+B)'=A'B' ,(AB)'=A'+B' and then trial and error 0 votes 0 votes Tendua commented Dec 8, 2016 reply Follow Share Mam, I think that the function is 1 on the minterms 0,1,2,4. so y' is definitely what you wrote but forgot to make the pos. You are counting max terms so it you should use pos term right. ? 0 votes 0 votes Sonu Kumar 1 commented Dec 1, 2017 reply Follow Share 7 NAND gates required 1 votes 1 votes Please log in or register to add a comment.
1 votes 1 votes There is a systematic procedure to find the number of NAND gates. First, determine the minimal SOP for ( AND-OR structure) then follow the steps-- no of gates=6 Epsilon95 answered Apr 20, 2017 Epsilon95 comment Share Follow See all 0 reply Please log in or register to add a comment.