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4 votes
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in Digital Logic 3.5k views

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7 votes
 
Best answer

Here we are getting output as Y'=A'BC+AB'C+ABC'+ABC

                                              =AB+BC+AC

                                             =((A(B'C')')' (BC)')'

So, total 6 NAND gates are required.

If complemented and uncomplemented variable both present then minimum NAND gates are 4


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0

Is there any method to reduce AB+BC+AC to ((A(B'C')')' (BC)')' ? 

0
No, just put demorgan law (A+B)'=A'B'  ,(AB)'=A'+B'

and then trial and error
0
Mam, I think that the function is 1 on the minterms 0,1,2,4. so y' is definitely what you wrote but forgot to make the pos. You are counting max terms so it you should use pos term right. ?
1
7 NAND gates required
1 vote

There is a systematic procedure to find the number of NAND gates.

First, determine the minimal SOP for ( AND-OR structure) then follow the steps--

no of gates=6

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