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Here we are getting output as Y'=A'BC+AB'C+ABC'+ABC

                                              =AB+BC+AC

                                             =((A(B'C')')' (BC)')'

So, total 6 NAND gates are required.

If complemented and uncomplemented variable both present then minimum NAND gates are 4

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There is a systematic procedure to find the number of NAND gates.

First, determine the minimal SOP for ( AND-OR structure) then follow the steps--

no of gates=6

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