Here we are getting output as Y'=A'BC+AB'C+ABC'+ABC
So, total 6 NAND gates are required.
If complemented and uncomplemented variable both present then minimum NAND gates are 4
Is there any method to reduce AB+BC+AC to ((A(B'C')')' (BC)')' ?
There is a systematic procedure to find the number of NAND gates.
First, determine the minimal SOP for ( AND-OR structure) then follow the steps--
no of gates=6