GATE CSE 2015 Set 2 | Question: 48

Question

A half adder is implemented with XOR and AND gates. A full adder is implemented with two half adders and one OR gate. The propagation delay of an XOR gate is twice that of an AND/OR gate. The propagation delay of an AND/OR gate is $1.2$ microseconds. A $4$-bit-ripple-carry binary adder is implemented by using four full adders. The total propagation time of this $4$-bit binary adder in microseconds is ______.

Comments

In Ripple carry adder, a stage doesn’t wait for the “full output” of previous stage. It only waits for the previous stage’s carry to reach to itself. Now, carry generated by our current stage can be written in 2 ways:-           

  1)Carry generated= $xy + $ $(x$$\bigoplus$$y)C_{in}$                2)Carry generated=  $xy+yC_{in} +xC_{in}$       where $C_{in}$ is carry received by our current stage

Using 1st way, delay in carry generation would be 4.8$us$  and  by using 2nd way, delay in carry generation would be 2.4$us$. So, answer should be according to 2.4$us$ delay(better than 4.8$us$ delay).

So, total delay will be $(4-1)*2.4 + 4.8$ = $12us$

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what will be the answer if it is carry look ahead adder?

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@swami_9

I think it will be $4.8\mu s$ only, as there is no need to wait for the carry from the prev. adder.

Answer 1

In Ripple carry adder, a stage doesn’t wait for the “full output” of previous stage. It only waits for the previous stage’s carry to reach to itself. Now, carry generated by our current stage can be written in 2 ways:-           

  1)Carry generated= $xy + $ $(x$$\bigoplus$$y)C_{in}$                2)Carry generated=  $xy+yC_{in} +xC_{in}$       where $C_{in}$ is carry received by our current stage

Using 1^st way, total time taken would be 19.2  and  by using 2^nd way, total time taken would be 12. So, answer should be 12 only(better than 19.2).

So, total delay will be $(4-1)*2.4 + 4.8$ = $12us$

Answer 2

In Ripple carry adder, a stage doesn’t wait for the “full output” of previous stage. It only waits for the previous stage’s carry to reach to itself. Now, carry generated by our current stage can be written in 2 ways:-           

  1)Carry generated= $xy + $ $(x$$\bigoplus$$y)C_{in}$                2)Carry generated=  $xy+yC_{in} +xC_{in}$       where $C_{in}$ is carry received by our current stage

Using 1st way, total time taken would be 19.2  and  by using 2nd way, total time taken would be 12. So, answer should be 12 only(better than 19.2).

So, total delay will be $(4-1)*2.4 + 4.8$ = $12us$

Answer 3

In Ripple carry adder, a stage doesn’t wait for the “full output” of previous stage. It only waits for the previous stage’s carry to reach to itself. Now, carry generated by our current stage can be written in 2 ways:-           

  1)Carry generated= $xy + $ $(x$$\bigoplus$$y)C_{in}$                2)Carry generated=  $xy+yC_{in} +xC_{in}$       where $C_{in}$ is carry received by our current stage

Using 1st way, total time taken would be 19.2  and  by using 2nd way, total time taken would be 12. So, answer should be 12 only(better than 19.2).

So, total delay will be $(4-1)*2.4 + 4.8$ = $12us$

Answer 4

The shortcut to answer such questions is:

Find out the Sum and Carry propagation time of 1 Full Adder and then use the formula :

Maximum propagation time = (n-1)[T(AND) + T(OR)] + max{T(sum),T(carry)} where n=number of bits of ripple carry adder.

So the answer is (4-1)(1.2+1.2) + 4.8 =12 microseconds.

Please note, that both T(sum) and T(carry) of the FA are coming 4.8 microseconds. So the max is 4.8 microseconds.