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In $2's$ complement addition, overflow

  1. is flagged whenever there is carry from sign bit addition
  2. cannot occur when a positive value is added to a negative value
  3. is flagged when the carries from sign bit and previous bit match
  4. None of the above
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3 Answers

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(B) is the answer. When a positive value and negative value are added overflow never happens. 

http://sandbox.mc.edu/~bennet/cs110/tc/orules.html

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   1 0 1 0     = -6

   0 1 1 0     = +6


1 0 0 0 0     =  0     


Here we add +ve and -ve no. which generate carry but it is not overflow i.e we can ignore it.

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  1. In 2′s complement addition,carry always doesn’t indicate overflow.

  2. When we will add a positive value (+a) with a negative value(-b). The result will be in between them means -b<= result <= +a. So overflow can not occur. As if we can represent -b and +a in some fixed number of bits then we can also represent any number between them.

      C. In 2′s complement addition, overflow is flagged when the carries from sign bit and previous bit did not match.                 i.e Cn⊕Cn−1=1.

      Answer: B

Answer:

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