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In $2's$ complement addition, overflow

  1. is flagged whenever there is carry from sign bit addition
  2. cannot occur when a positive value is added to a negative value
  3. is flagged when the carries from sign bit and previous bit match
  4. None of the above
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Overflow condition can be written in any of the three ways – 

  1. $C_{n} \oplus C_{n-1}=1$ which says that either 1st MSB or 2nd MSB should give carry but not both.
  2. $A_{n}B_{n}\bar{C_{n-1}} + \bar{A_{n}}\bar{B_{n}}C_{n-1}=1$ where $A_n$ and $B_n$ are the MSB (which are sign bits) and $C_{n-1}$ is the carry from the 2nd MSB.
  3. $A_{n}B_{n}\bar{R_{n}} + \bar{A_{n}}\bar{B_{n}}R_{n}=1$ where $R_{n}$ is the MSB (sign bit) of result of the addition.

From the third condition above, we can see that overflow will happen when:

 1. $A_n,B_n$ is 0 (which means positive numbers) and $R_n$ is 1 (which means a negative number).

2. $A_n,B_n$ is 1 (which means both are negative numbers) and $R_n$ 0 (which means a positive number).

Conclusion: For overflow to happen, two positive numbers are added and the result is negative OR two negative numbers are added and the result is positive.

PS: 2nd result can be derived from 1st result by replacing the value of $C_n$ with $A_nB_n + C_{n-1}(A_n \oplus B_n)$ and 3rd result can be derived from the 2nd result by thinking a bit. Let me know if you find it difficult to derive it.

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2 Answers

41 votes
 
Best answer

(B) is the answer. When a positive value and negative value are added overflow never happens. 

http://sandbox.mc.edu/~bennet/cs110/tc/orules.html

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5 Comments

Overflow can when 2 postive value are added and it result in a negative value and vice versa . so overflow falg is set .
5
means?
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Sir , in case of unsigned numbers .. 2's complement addition of a positive and negative number can yield an overflow .

Here nothing is given about signed or unsgned numbers .. so what will be the answer ?

None of the above?
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In Morris mano, it is given that in case of signed numbers overflow can occur when the carry from priveous bits and current bits are different...
3
positive value is added with negative value, i.e it's a 2's complement substraction & In 2's complement substraction, carry can come out, but this carry doesn't indicate overflow, as it's on 2's complement.

This is the flow of logic here ???
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4 votes

 

   1 0 1 0     = -6

   0 1 1 0     = +6


1 0 0 0 0     =  0     


Here we add +ve and -ve no. which generate carry but it is not overflow i.e we can ignore it.

Answer:

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