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+12 votes

In $2's$ complement addition, overflow

  1. is flagged whenever there is carry from sign bit addition
  2. cannot occur when a positive value is added to a negative value
  3. is flagged when the carries from sign bit and previous bit match
  4. None of the above
asked in Digital Logic by Veteran (59.6k points)
edited by | 1.6k views

1 Answer

+32 votes
Best answer

(B) is the answer. When a positive value and negative value are added overflow never happens.

answered by Veteran (362k points)
selected by
Overflow can when 2 postive value are added and it result in a negative value and vice versa . so overflow falg is set .
Sir , in case of unsigned numbers .. 2's complement addition of a positive and negative number can yield an overflow .

Here nothing is given about signed or unsgned numbers .. so what will be the answer ?

None of the above?
In Morris mano, it is given that in case of signed numbers overflow can occur when the carry from priveous bits and current bits are different...

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