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Consider a non-pipelined processor with a clock rate of $2.5$ $GHz$ and average cycles per instruction of four. The same processor is upgraded to a pipelined processor with five stages; but due to the internal pipeline delay, the clock speed is reduced to $2$ $GHz$. Assume that there are no stalls in the pipeline. The speedup achieved in this pipelined processor is_______________.
in CO and Architecture by Boss (30.8k points)
edited by | 9.9k views
+1
Speedup = ExecutionTime
Old / ExecutionTimeNew ExecutionTimeOld = CPIOld * CycleTimeOld [Here CPI is Cycles Per Instruction] = CPIOld * CycleTimeOld = 4 * 1/2.5 Nanoseconds = 1.6 ns Since there are no stalls, CPUnew can be assumed 1 on average. ExecutionTimeNew = CPInew * CycleTimenew = 1 * 1/2 = 0.5 Speedup = 1.6 / 0.5 = 3.2
+3

In non-pipelined processor for each 1.6ns one instruction will be processed.
In the equivalent pipelined processor, when pipeline is full, for each .5ns one instruction will be processed.

Speedup of pipeline processing over non-pipeline processing = $1.6/.5 = 3.2$

Pipeline processing is $3.2$ time faster than non-pipelining processing.

4 Answers

+76 votes
Best answer

Answer = 3.2.

To compute cycle time, we know that a $2.5\text{ GHz}$ processor means it completes $2.5\text{ billion}$ cycles in a second. So, for an instruction which on an average takes $4$ cycles to get completed, it will take $\dfrac{4}{2.5}\ $ nanoseconds. 

On a perfect pipleline (i.e., one which has no stalls) $CPI = 1$ as during it an instruction takes just one cycle time to get completed.

So,

Speed Up $=\dfrac{\text{Old Execution Time of an Instruction}}{\text{New Execution Time of an Instruction}}$

$=\dfrac{CPI_{\text{old}}/CF_{\text{old}}}{CPI_{\text{new}}/CF_{\text{new}}}$

$=\dfrac{4/2.5\ GHz}{1/2\ GHz}$

$=3.2$

by Active (1.4k points)
edited by
0
@amarVashishth So, even if we use 4 or 6 stage pipeline answer is same?
0

that will depend on what the question says. 
Here by introducing a 5 stage pipelining, though successful, the processor speed is reduced to 2GHz.

0
clock speed is reduced to handle buffer delays. Also how can you say in 1 clock cycle an instruction gets completed with pipeline? It should be the max clock cycle(s) needed for any stage.
+2

Yes, you are right.

It has been encountered many times that whenever they suggest something like a pipelined-processor with no stalls we assume that we are talking about a Scalar processor.

check : https://en.wikipedia.org/wiki/Cycles_per_instruction#Explanation

0
yes, but I don't consider that a safe assumption. Moreover I very much doubt if the same question repeats answer will be 3.2..
+2

Sir, but I also have a second thought on this.

Consider a pipelined-processor where CPI = 3, say EX stage takes 3 cycles and all other takes up just one.
the second instruction that enters the pipeline stalls at stage just behind the EX stage, it means there were stall cycles for that instruction.

But here, we are given that there are No stall cycles. Hence, we can say that the instruction flow from present stage to the next on each clock cycle. Hence, CPI has to be 1.

0
I think I got the issue- the execution time of an instruction with pipeline cannot go below a clock cycle (as we can not assume super scalar). This will give answer as 3.2 and that should be the reason. With a 3 stage pipeline, the same approach won't work here.
0

Sir, How is a stall cycle not possible when $CPI>1$?

0
Suppose each stage takes 2 clock cycles, there won't be any stall.
0

Pipeline stall is a delay in execution of an instruction. The instruction waiting just outside the pipeline will experience stall cycles.

0
every stage is taking same cycles- so there will be no delay..
+4
for GATE syllabus we cover Classic RISC pipeline only, In which if it's a successful pipeline we have CPI = 1. Which is an objective of this pipeline.

 

"If every cycle takes up same number of cycles then there will be no delay" does this imply that there are no Stall Cycles?
If yes, then stalls do happen even when stages are always busy, this can be understood by taking example of a branch instruction.
0
yes for ideal piepline CPI is considered as 1
0
@arjun sir,what is meant by the ideal case that CPI =1?

does it mean that clock cycle to execute one instruction =1 or clock cycle for every stage =1?

and if it means that 1 clock cycle to execute an instruction then how is it possible that a single intruction needs only 1 clock cycle because there are many stages in between which are having their cycles
+1
how can you say that there are no stalls when stages have equal cycles?

lets suppose 2cycles for each IF,ID,EX,WB

then

IF IF ID ID EX EX WB WB

-  -    IF IF  ID  ID   EX  EX WB WB

        -   -   IF   IF   EX  EX  WB  WB

CONSIDER ABOVE EXAMPLE,I AM FACING TWO CYCLE STALLS PER INSTRUCTION HERE...
0

@arjun Sir, So we need not worry about $\text{one stage time} > \text{new cycle time}$  situation?

0
yes we only consider CPI > or =1
+5

@Akriti

CPI means Cycle Per Instruction. It is defined as no of cycle that is required to execute one instruction. It has nothing to do with the clock cycle of stage. 

In pipeline CPI=1 means that every 1 cycle one instruction is getting out of the pipeline.Though it seems that each instruction is getting out of pipeline after 1 cycle, it does not means stages of pipeline has done the computation in 1 cycle ..they all took 1 cycle each.. However due to being overlapped with other instruction, it appears that each instruction are taking 1 cycle (but actually each instruction took (k stage)*(1 cycle) )

Q. how can you say that there are no stalls when stages have equal cycles?

Stalls in pipeline occurs due to hazards  only. 

Stages of pipeline can take different cycles but to solve the problem we assume in pipeline , Cycle'=max(cycle 1, cycle 2 ...cycle k) where cycle k=cycle need for stage k.

If you use take cycle 1=cycle 2 =.... =cycle k (case where each stages take equal cycles)

then Cycle'=cycle1. Now you can see there wont be any stalls until any hazards occurs.

What i mean is , stall means waiting . So we stall only when we have a work to do but since the data is not available or resource is not available or next instruction to excute is not clear, we cant proceed. Hence we have to wait a bit i.e. stall for cycle till we get our requirement fullfilled .

+3

CPIpipelined = Ideal CPI + Pipeline stall clock cycles per instruction

= 1 + Pipeline stall clock cycles per instruction(it is given to be 0)

=1+0

=1

Source:-

http://web.cs.iastate.edu/~prabhu/Tutorial/PIPELINE/hazards.html

0

@srestha

CPI > or <?? What it should be?

0
where u got less than?
0
Oh, actually I remember now, that was in the case of superscalar.

For gate we don't have that.
0

@naresh1845 @Arjun Sir @amarVashishth

How an instruction can take $\frac{4}{2.5} Gs$

Didn't get this

0

What is CF here?

@naresh1845

+1

@Arjun Sir.

There is definitely a mistake in this best answer, perhaps the typo maybe.

It should be:

On an average takes 4 cycles to get completed will take $\frac{4}{2.5} \;\bf{nano}\; seconds$

+1
Is it fine now?
0
Yes sir its perfect now.

Thanks for making corrections.
+8

$\color{blue}{\underline{\textbf{For Non-Pipelined System:}\Rightarrow}}$

Given frequency $\mathbf{ = 2.5 GHz}$

$\therefore 1\; \text{Cycle time} = \mathbf{\dfrac{1}{2.5Gs} }= \dfrac{1}{2.5}\;\text{nano seconds}$

$\therefore \text{Total Time}  = 4\times \frac{1}{2.5} \text{nano seconds} =\dfrac{4}{2.5}\;\text{nano seconds}$

$\color{blue}{\underline{\textbf{For Pipelined System:}\Rightarrow}}$

 $\textbf{Average CPI} = 1\;\;[\because \text{It is given that pipeline has no stalls.}]$

This also proves the fact that pipeline is also $\color{magenta}{\text{independent of the number of phases}}$, [so there would be $\color{red}{\text{no change}}$ if the question was asked for $\mathbf 6$ stages also.]

Similarly, as above:

$\mathbf{Frequency = 2\;GHz}$

$\therefore\;1\text{ cycle time} =\dfrac{1}{2} \;\text{nano seconds}$

$\therefore \textbf{Speed-up} = \dfrac{\text{Time without pipelining}}{\text{Time with pipelining}} = \dfrac{\dfrac{4}{2.5}}{\dfrac{1}{2}} = 3.2$

+1
Yes its correct.
0
Thanks
+32 votes

Speed up $=\dfrac{\text{Old execution time}}{\text{New execution time}}$

Old execution time $=\dfrac{\text{CPI}}{2.5} =\dfrac{4}{2.5}=1.6\text{ ns}$

With pipelining,

$=\dfrac{\text{each instruction needs old execution time} \times \text{old frequency}}{\text{new frequency (without pipelining)}}$

$=\dfrac{1.6\times 2.5}{ 2}=2\text{ ns}$

There are $5$ stages and when there is no pipeline stall, this can give a speed up of up to $5$
(happens when all stages take same number of cycles).
In our case this time will be $\dfrac{2}{5}= 0.4\text{ ns}$.
But clock frequency being $2\text{ GHz},$ clock cycle is $\dfrac{1}{2}\text{ GHz}=0.5\text{ ns}$
and a pipeline stage cannot be faster than this.

So, average instruction execution time after pipelining $\text{= max (0.4, 0.5) = 0.5 ns}$.

So, speed up compared to non-pipelined version $=\dfrac{1.6}{0.5}= 3.2$

by Veteran (431k points)
edited by
0
??
0

With pipelining, each instruction needs old execution time * old frequency/new frequency = 1.6 * 2.5 / 2 = 2 ns (without pipelining)

0
why considering 100 instruction execution for both my answer is different . i sometime have problem solving using 1 instruction execution time. what i do is consider 100 instruction. so if i assume here 100 instruction

then t will be 160/52 = 3.07. why i am not correct if i consider 100 instruction. is my approach right .

$\frac{100*\frac{4}{2.5}}{104*\frac{1}{4}}$
+1

@Arjun Sir

(old execution time * old frequency/new frequency )without pipelining Execution Time= 1.6 * 2.5 / 2 = 2 ns

 rt?

In our case this time will be 2/5 = 0.4 ns

means though maximum speed up could be 5, we are only using 2 ns within 5.rt?

But clock frequency being 2 GHz, clock cycle is 1/2 GHz = 0.5 ns

means execution time 1/f, But there is no stalls in the pipeline,which also a cause, that execution time will be 0.5ns(As, we know, CPI/clock cycle =execution time).

So, max (execution time of nonpipeline system, execution time due to 2 GHz frequency)

 u have taken .

But why do u think it will be more accurate, though it will get directly from the formula =(CPI/clock cycle)

0
sir i am not getting all this ?? can you plz conclude /brief in  as confused about ur solution and naresh solution and one of my teacher told be If CPI is not given in case of pipeline than we can take it 1 plz coments as few lines so that if questions come again i able to answer n differentiate.
0

@arjun,

With pipelining, each instruction needs old execution time * old frequency/new frequency (without pipelining) = 1.6 * 2.5 / 2 = 2 ns

can you explain this statement? i did not understand the calculation part. 

i know execution time=(CPI/clock rate). But how you are calculating the new execution time here? Please explain?

+1

Let initial processor with 2.5Ghz is P1 and new processor with 2Ghz is P2. 

Old execution time = CPI/2.5 = 4/2.5 = 1.6 ns

This is the usual equation, you all know about it.

With pipelining, each instruction needs old execution time * old frequency/new frequency (without pipelining) = 1.6 * 2.5 / 2 = 2 ns
 

P1 is upgraded to P2 but still non-pipelined, so the above equation into play again as
Execution Time=old CPI/New Frequency which is 4/2=2ns.

(sir has done that putting old values as ((4/2.5)*2.5)/2=2ns).

{Section-1}
P2 becomes pipelined and we know when we upgrade our processor from non-pipelined to pipelined we achieve a speedup of "number of stages" we have in the pipeline, i.e. 5, over non-pipelined P2.

There are 5 stages and when there is no pipeline stall, this can give a speed up of up to 5 (happens when all stages take same number of cycles). In our case this time will be 2/5 = 0.4 ns. But clock frequency being 2 GHz, clock cycle is 1/2 GHz = 0.5 ns and a pipeline stage cannot be faster than this. 

So, what will be the new execution time?
It will be obtained by the formula of speed up,
 i.e. Speed up =Old time/new time 
So, New time=Speed Up/Old time
                    =2/5=0.4 nsec.


{Section-1 Ends}

What happened in section-1 is we calculated pipelined processor P2 cycle time from its non-pipelined format.

Now, we calculate Cycle time of pipelined processor P2 like we usually do, In ideal pipeline, CPI is 1, and given clock rate is 2Ghz.
Execution time = CPI/clock rate
                       =1/2=0.5 nsec

Why there is a difference in the two execution time of the same processor when pipelined. I don't know exactly, may be arjun sir clarify this point. But I can say that the method we are using in section-1 is considering CPI=4 for non-pipeline of P2 as this CPI of old P1, it might happen P1 would have less number of stages than P2, which change the non-pipelined CPI of P2.

If above statement is confusing we can also look at this our new processor P2 has 5 stages if each stage takes 1-cycle time so our new CPI will be 5 which is greater than P1.
As CPI increase in equation Execution time=CPI/clock rate the time execution time increased. remember we still talking about the non-pipelined processor.

but as soon the processor become pipeline its Ideal CPI becomes 1 as at every clock cycle it produces one output. So we can calculate P2 another way which gave an answer as 0.5 nsec.    

So, average instruction execution time after pipelining = max (0.4, 0.5) = 0.5 ns. 

Everything is working in sequence like P1 non-pipe -> becomes P2 Non-pipe -> from which we calculate P2 pipe execution time -> then we calculate P2 pipe execution time again with default method-> compare both of these -> Max is chosen(don't know why?).

SpeedUp= Non-pipelined of P1/Pipelined of P2
             =1.6/0.5
             =3.2

0
@bhuv I had already given the reason for it -- a pipeline stage cannot run faster than a clock cycle.
+5 votes

Non Pipeline: Given $2.5$ GHz, CPI=$4$

$1$ sec ---> $2.5 * 10^{9} $cycles

$1$ cycle  --->$ \frac{10}{25}$ ns

$1$ inst ---> $4$ clock cycle -->$ 4* \frac{10}{25} = \frac{8}{5}$ns

Pipeline: Given $2$ GHz, CPI= $1$

$1$ sec ---> $2* 10^{9} $ cycles

$1$ cycle  ---> $\frac{1}{2}$ ns

$1$ inst ---> $1$clock cycle -->$\frac{1}{2}$ns

Speedup = $\frac{Time\ in\ Non\ pipeline}{Time\ in\ Pipeline}$

Speedup=$ \frac{8}{5} * 2 = 3.2$

by Boss (16.4k points)
edited by
+1
this is under ideal condition? else with pipeline time would be Time for First inst + time for n-1 inst

i.e 4*0.5+0.5=2.5 but under ideal condition 0.5*1=0.5

am i correct?
+1

@

I think in given question they mentioned $"No$  $Stalls",$So we take ideal condition. 

0 votes

$\underline{\textbf{Answer:}\Rightarrow}$

$\underline{\textbf{Explanation:}\Rightarrow}$

$\color{blue}{\underline{\textbf{For Non-Pipelined System:}\Rightarrow}}$

Given frequency $\mathbf{ = 2.5 GHz}$

$\therefore 1\; \text{Cycle time} = \mathbf{\dfrac{1}{2.5Gs} }= \dfrac{1}{2.5}\;\text{nano seconds}$

$\therefore \text{Total Time}  = 4\times \frac{1}{2.5} \text{nano seconds} =\dfrac{4}{2.5}\;\text{nano seconds}$

$\color{blue}{\underline{\textbf{For Pipelined System:}\Rightarrow}}$

 $\textbf{Average CPI} = 1\;\;[\because \text{It is given that pipeline has no stalls.}]$

This also proves the fact that pipeline is also $\color{magenta}{\text{independent of the number of phases}}$, [so there would be $\color{red}{\text{no change}}$ if the question was asked for $\mathbf 6$ stages also.]

Similarly, as above:

$\mathbf{Frequency = 2\;GHz}$

$\therefore\;1\text{ cycle time} =\dfrac{1}{2} \;\text{nano seconds}$

$\therefore \textbf{Speed-up} = \dfrac{\text{Time without pipelining}}{\text{Time with pipelining}} = \dfrac{\dfrac{4}{2.5}}{\dfrac{1}{2}} = 3.2$

$\therefore\;\mathbf{3.2}$ is the correct answer.

by Boss (19.2k points)
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