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Consider a non-pipelined processor with a clock rate of $2.5$ gigahertz and average cycles per instruction of four. The same processor is upgraded to a pipelined processor with five stages; but due to the internal pipeline delay, the clock speed is reduced to $2$ gigahertz. Assume that there are no stalls in the pipeline. The speedup achieved in this pipelined processor is_______________.
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98 votes

Answer = 3.2.

To compute cycle time, we know that a $2.5\;\textsf{GHz}$ processor means it completes $2.5\;\text{billion}$ cycles in a second. So, for an instruction which on an average takes $4$ cycles to get completed, it will take $\dfrac{4}{2.5}\ $ nanoseconds. 

On a perfect pipleline (i.e., one which has no stalls) $\text{CPI} = 1$ as during it an instruction takes just one cycle time to get completed.

So,

Speed Up $=\dfrac{\text{Old Execution Time of an Instruction}}{\text{New Execution Time of an Instruction}}$

$=\dfrac{\text{CPI}_{\text{old}}/\text{CF}_{\text{old}}}{\text{CPI}_{\text{new}}/\text{CF}_{\text{new}}}$

$=\dfrac{4/2.5\;\textsf{GHz}}{1/2\;\textsf{GHz}}$

$=3.2$

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36 votes
36 votes

Speed up $=\dfrac{\text{Old execution time}}{\text{New execution time}}$

Old execution time $=\dfrac{\text{CPI}}{2.5} =\dfrac{4}{2.5}=1.6\text{ ns}$

With pipelining,

$=\dfrac{\text{each instruction needs old execution time} \times \text{old frequency}}{\text{new frequency (without pipelining)}}$

$=\dfrac{1.6\times 2.5}{ 2}=2\text{ ns}$

There are $5$ stages and when there is no pipeline stall, this can give a speed up of up to $5$
(happens when all stages take same number of cycles).
In our case this time will be $\dfrac{2}{5}= 0.4\text{ ns}$.
But clock frequency being $2\text{ GHz},$ clock cycle is $\dfrac{1}{2}\text{ GHz}=0.5\text{ ns}$
and a pipeline stage cannot be faster than this.

So, average instruction execution time after pipelining $\text{= max (0.4, 0.5) = 0.5 ns}$.

So, speed up compared to non-pipelined version $=\dfrac{1.6}{0.5}= 3.2$

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8 votes

Non Pipeline: Given $2.5$ GHz, CPI=$4$

$1$ sec ---> $2.5 * 10^{9} $cycles

$1$ cycle  --->$ \frac{10}{25}$ ns

$1$ inst ---> $4$ clock cycle -->$ 4* \frac{10}{25} = \frac{8}{5}$ns

Pipeline: Given $2$ GHz, CPI= $1$

$1$ sec ---> $2* 10^{9} $ cycles

$1$ cycle  ---> $\frac{1}{2}$ ns

$1$ inst ---> $1$clock cycle -->$\frac{1}{2}$ns

Speedup = $\frac{Time\ in\ Non\ pipeline}{Time\ in\ Pipeline}$

Speedup=$ \frac{8}{5} * 2 = 3.2$

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$\underline{\textbf{Answer:}\Rightarrow 3.2}$

$\underline{\textbf{Explanation:}\Rightarrow}$

$\color{blue}{\underline{\textbf{For Non-Pipelined System:}\Rightarrow}}$

Given frequency $\mathbf{ = 2.5 GHz}$

$\therefore 1\; \text{Cycle time} = \mathbf{\dfrac{1}{2.5Gs} }= \dfrac{1}{2.5}\;\text{nano seconds}$

$\therefore \text{Total Time}  = 4\times \frac{1}{2.5} \text{nano seconds} =\dfrac{4}{2.5}\;\text{nano seconds}$

$\color{blue}{\underline{\textbf{For Pipelined System:}\Rightarrow}}$

 $\textbf{Average CPI} = 1\;\;[\because \text{It is given that pipeline has no stalls.}]$

This also proves the fact that pipeline is also $\color{magenta}{\text{independent of the number of phases}}$, [so there would be $\color{red}{\text{no change}}$ if the question was asked for $\mathbf 6$ stages also.]

Similarly, as above:

$\mathbf{Frequency = 2\;GHz}$

$\therefore\;1\text{ cycle time} =\dfrac{1}{2} \;\text{nano seconds}$

$\therefore \textbf{Speed-up} = \dfrac{\text{Time without pipelining}}{\text{Time with pipelining}} = \dfrac{\dfrac{4}{2.5}}{\dfrac{1}{2}} = 3.2$

$\therefore\;\mathbf{3.2}$ is the correct answer.

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