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+16 votes

The performance of a pipelined processor suffers if:

  1. the pipeline stages have different delays
  2. consecutive instructions are dependent on each other
  3. the pipeline stages share hardware resources
  4. All of the above
asked in CO & Architecture by Veteran (59.5k points)
edited by | 2.2k views

2 Answers

+23 votes
Best answer

Answer is D.

A: Yes. Total delay = Max (All delays) + Register Delay.

B: Yes, if data forwarding is not there.

C: Yes, like ID and EX shares ID/EX register.

answered by Boss (34.1k points)
edited by
can same register access cause structural hazard??
for c option it could be register (same) with renaming ..? structural hazard ?
i think yes

structural hazard due to resource conflict, a resource can be register or memory
Well, the register file has SEPARATE input and output ports (Hamacher 6th edition, chapter 5), so how register file can cause resource confilct ?
+7 votes
Option D)All Of The Above.

Pipeline suffer from options:-

A) Yes, As pipeline need to work in SYNC all stage should operate in same time. If there are stages taking different time, if there is a slower stage, all faster stage will be bottlenecked by the cycles the slowest stage takes.

B)Yes, As there could be DATA HAZARDS.
           eg: SUB R2,R4,R5
                 ADD R6,R2,R4 //here register r2 result will be dependent on first instruction.

C)Yes, IF(Instruction Fetch) and MEM(Main Memory) stage can cause STRUCTURAL HAZARDS and there may be a chance that both stages need Memory simultaneously, that's why many Arch. slipt the cache as INST cache and Data Cache.
answered by Active (3.7k points)
edited by

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