From wikipedia (third paragraph),
By tying the output of several open collectors together, the common line becomes a "wired AND" (positive-true logic) or "wired OR" (negative-true logic) gate. A "wired AND" behaves like the boolean AND of the two (or more) gates in that it will be logic 1 whenever (all) are in the high impedance state, and 0 otherwise. A "wired OR" behaves like the Boolean OR for negative-true logic, where the output is LOW if any of its inputs are low.
So, after tying the open-collector NAND Gates, the common line becomes a wired AND.
So, $Y = \left(\overline{ABC}\right) \cdot \left(\overline{DE}\right)$
By D’ Morgan’s law, $Y = \overline{ABC + DE}$
Hence,
Correct Answer: Option (B)