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A single bus CPU consists of four general purpose register, namely, $R0, \ldots, R3, \text{ALU}, \text{MAR}, \text{MDR}, \text{PC}, \text{SP}$ and $\text{IR}$ (Instruction Register). Assuming suitable microinstructions, write a microroutine for the instruction, $\text{ADD }R0, R1$.
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MAR ←  PC
PC    ←  PC +3
MDR ←  MEM[MAR]
IR     ←  MDR
MAR ← MAR+1
MDR ← MEM[MAR]
R0    ← MDR
MAR ← MAR +1
MDR ← MEM[MAR]
R1    ← MDR
R0    ← R0+R1

Reference: CPU Datapath Diagram from Hamacher

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