There may be 2 scenarios to this which is discussed below :
So in 1st case , no of cycle required = 17
in 2nd case , no of cycle required = 14
Specifically 2nd case deals with RISC pipeline..
And 1st case deals with an arbitrary 5 stage pipelined processor..
So according to the question , it is case 1..
Hence the correct answer should be 17 cycles..