Self Made

Question

In pipelining, what is the need of interstate buffer?

We are anyway setting the clock equal to the longest delay. The output of one stage will not come out untill the end of one clock cycle.

So why do we need the buffer?

Comments

Interstate buffers are required in pipelined system to enable the feature of operand forwarding in a pipeline..Else more stall cycles will occur possibly due to RAW hazard(data dependency)

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So, the output due to operand forwarding is stored in the buffers first?

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Operand forwarding is done between EX stage and ID stage ..So say the current instruction wants to read data of earlier instruction which has not yet written result i.e. not performed WB stage till now bt EX stage completed..Then the buffer at the end of EX stage can pass its data to the ID stage of the current instruction..

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Thanks.