retagged by
467 views
0 votes
0 votes

A computer uses a small direct-mapped cache between the main memory and the processor. The cache has four $16$-bit words (the data field), and each word has an associated $13$-bit tag field. When a miss occurs during a read operation, the requested word is read from the main memory and sent to the processor. At the same time, it is copied into the cache, and its block number is stored in the associated tag.

Consider the following loop in a program where all instructions and operands are $16$ bits long:

$$ \begin{array}{|c|c|c|} \hline \text{LOOP} & \text{Add} & \text{(RI)+, RO} \\ \hline & \text{Decrement} & R2 \\ \hline & \text{BNE} & \text{LOOP} \\ \hline \end{array}$$

Main memory contents:

$$ \begin{array}{|c|c|c|} \hline \text{Address} & \text{Data} \\ \hline \text{054E} & \text{A03C} \\ \hline & \text{05D9} \\ \hline & \text{10D7}\\ \hline \end{array}$$

Assume that before this loop is entered, registers $R0,  Rl$, and $R2$ contain $0, 054E$ and $3$, respectively. Also assume that the main memory contains the data shown in the above diagram of Main memory contents, where all entries are given in hexadecimal notation. The loop starts at location $\text{LOOP }= 02EC$. 

What is the number of Main memory access at the end of the First pass through the loop?

  1. $3$
  2. $4$
  3. $6$
  4. $8$
retagged by

1 Answer

Best answer
4 votes
4 votes
In the first pass there are 3 instructions and one data access. So, totally 4 memory accesses (each of 16 bits)

Add                (Rl)+,  RO
$$ \begin{array}{|c|c|c|} \hline \text{Add} & \text{(RI)+ , RO} \\ \hline \end{array}$$
This means, Content of memory location given in R1 is added to R0, and then R1 is incremented (to point to next location).
edited by
Answer:

Related questions

1 votes
1 votes
3 answers
3