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Consider the following program segment for a CPU having three Registers $R1, R2,$ and $R3$:

$$\begin{array}{|l|l|l|} \hline \text{Instruction} & \text{Operation} & \text{Instruction } \\ {} & {} & \text{Size In words} \\ \hline \text{MOV R1,200} & R1\leftarrow[200] & 2 \\ \hline \text{ADD R2,R1} & R2\leftarrow R2 + R1 & 1 \\ \hline \text{MUL R3,R1} & R3\leftarrow R3 \:\ast R1 & 1 \\ \hline \text{MOV 200,R3} & M[200]\leftarrow R3 & 2 \\ \hline \text{HALT} & \text{Machine Halts} & 1 \\ \hline \end{array}$$

The memory is byte-addressable with word size $2 Bytes$, and the program is loaded starting from memory location $200$. If an interruption occurs while the ‘Multiply’ instruction is being executing by the CPU, then the return address saved onto the stack will be _______.

1st Instruction requires 2 *16 bit = 4 byte
2nd instruction requires 1 *16 = 2 byte
3rd instruction requires  1* 16 = 2 bytes
So 1st  Instruction  goes from 200 to  203 address/ memory location
2nd instruction goes from 204 to 205 memory location
3rd instruction goes from  206 to 207  memory location
So the starting address of 4th instruction  208 will be stored on the top of the stack.
by
     __________
200 |          |
201 |   MOV    |
202 |          |
203 |__________|
205 |__________|
206 |   MUL    |
207 |__________|
208 |   ...    |
.
.

Program will be saved in memory like this. Each word is 2 bytes long, and each instruction takes either 1 word or 2 word as given in the table. And the memory is byte addressable, so every byte should be given separate addresses.

Whenever an interrupt occurs during an instruction, that instruction is completed and then the interrupt is addressed.

So, the return address is 208, i.e. next instruction after MUL.

So contents of PC are in Bytes.

While executing MUL at 206th Byte, PC points to next instruction, ie at 208th Byte. (Answer)

When the interrupt occurs, the Program Status Word, along with contents of PC is saved onto the stack.

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