This is a 4-bit Synchronous Binary Up Counter
Here, each Flip flop get clock pulse at the same time. So, when the clock is applied, in 25 nsec all 4 flip-flop will give output + we need inputs for the next stage of flip-flops so additional 5 nsec + 5 nsec (two AND gates) will be needed. So, minimum time period needed for clock is 25 + 5 + 5 = 35 nsec.
According to ques. for MOD-256 counter we need 8 flip-flops
$\therefore$ we need (8-2) AND gates in series connection (as mentioned two input AND gates only)
$F\_{clk}$ $= \frac{1}{T_{FF} + (8-2) T_{gate}}\\ = \frac{1}{25 + (8 -2) 5 }\\ = 0.01818 \times 10^{9}\\ = 18.18\ \ MHZ$