# ME test

14 votes
1.7k views
For synchronous series counter of modulus 256, the propagation delay for each flip flop is 25 nsec and propagation delay of each two input AND gate is 5 nsec. What is the maximum frequency of the MOD256 counter ? (in MHz)

retagged

## 2 Answers

17 votes

Best answer

This is a 4-bit Synchronous Binary Up Counter

Here, each Flip flop get clock pulse at the same time. So, when the clock is applied, in 25 nsec all 4 flip-flop will give output + we need inputs for the next stage of flip-flops so additional 5 nsec + 5 nsec (two AND gates) will be needed. So, minimum time period needed for clock is 25 + 5 + 5 = 35 nsec.

According to ques. for MOD-256 counter we need 8 flip-flops
$\therefore$ we need (8-2) AND gates in series connection (as mentioned two input AND gates only)

$F\_{clk}$ $= \frac{1}{T_{FF} + (8-2) T_{gate}}\\ = \frac{1}{25 + (8 -2) 5 }\\ = 0.01818 \times 10^{9}\\ = 18.18\ \ MHZ$

selected by
0
explain the formula how?
5

@lokesh here i think ur problem how to get time period so i try to explain.. here propagation delay of FF  is taken  and also in question given that  2 - input AND gate so here if we design that in initial first two FF doesn't required any AND gate but AND gate is required from third FF because it takes a 2-input FF from FF1 and FF2  so that here initial FF1 and FF2 not reqiured any FF other than all FF required FF so here total  n-FF so i substract two FF.   so its final (n-2) * Tpd(AND)..i hope it help u

0
0
ty Anirudh! I was considering AND gate for output
0

@Hradesh patel Any valid reference for the above formula, other than Made Easy ?

1

@Kapil see the first binary up counter in this link

https://www.doc.ic.ac.uk/~nd/surprise_96/journal/vol4/cwl3/report.html#design

assume initial state 0000 now when a clock is applied we need 25ns to get DCBA rt?

then we have to give 5ns + 5ns for generating inputs for FFs for next state rt?

that means 25+ 5 + 5 = 35 ns rt?

0
caz both AND gates are connected in series so we need to add each AND gate delay
0

Right !! I missed the word series

and took it as parallel counter . In case of parallel counter, it will be $33.33$ MHZ.

0
what about the other ques??
1
You have commented there, Arjun Sir will check that. That one is also is also a case of series counter.
0
@Hradesh Patel, how it can be 4 bit counter, as it is given that it should ne mod256, How it can be 4 bit, please explain
4 votes

Propagation Delay for Synchronous counter does not depend on the no of flip flops because in sychronous counter clock is applied to each flip flop at the same time .

so Propagation delay of Synchronous counter = Propagation delay of Flip flop + delay due to combination circuit

= 25 nsec + 5 nsec =30 nsec

So frequency = 1/ Time period = 1/30ns =33.33 MHZ

Not exact duplicate question ;- https://gateoverflow.in/26442/gate1991_5-c

edited by
0
ans to ques given in made easy is 18.18
0

How ?
Anirudh  kindly have a look

0
I didnt understood the given ans...they considered (n-2) AND gates and I dont know how and which??
0

with one single gate you cannot count till 256 ryt?

http://www.allaboutcircuits.com/textbook/digital/chpt-11/synchronous-counters/

0
Amit in case of asynchronous counter we will add the delay of all ffs right? Suppose the same question was replaced with asynchronous  then wat would be the answer?
1

this answer contradicts https://gateoverflow.in/26442/gate1991_5-c

both are series connection.In the link i shared only one gate delay considered but in the current question we are taking all?

0
@rahul sharma 5 , I think that answer will be 1/30 only here because that is the way synchronous counters work.
If it would have been asynchronous then answer will be 1/(6*5 + 8*25). Did you find any information regarding this ?
0
How are you getting 1/30?

## Related questions

0 votes
0 answers
1
234 views
2 votes
2 answers
2
230 views
0 votes
1 answer
3
48 views
A $4$ bit ripple counter and a $4$ bit synchronous counter are made using flip-flops having a propagation delay of $10$ ns each. If the worst case delay in the ripple counter and the synchronous counter be $R$ and $S$ respectively, then $R = 10$ ns, $S = 40$ ns $R = 40$ ns, $S = 10$ ns $R = 10$ ns, $S = 30$ ns $R = 30$ ns, $S = 10$ ns
0 votes
0 answers
4
21 views
A $4$ bit ripple counter and a $4$ bit synchronous counter are made using flip-flops having a propagation delay of $10$ ns each. If the worst case delay in the ripple counter and the synchronous counter be $R$ and $S$ respectively, then $R = 10$ ns, $S = 40$ ns $R = 40$ ns, $S = 10$ ns $R = 10$ ns, $S = 30$ ns $R = 30$ ns, $S = 10$ ns