1 votes 1 votes A 4-bit synchronous counter uses flip-flops with propagation delay times of $15$ ns each. The maximum possible time required for change of state will be _____. $15$ ns $30$ ns $45$ ns $60$ ns Digital Logic tbb-digital-logic-2 + – Bikram asked Nov 26, 2016 edited Aug 19, 2019 by Counsellor Bikram 452 views answer comment Share Follow See all 0 reply Please log in or register to add a comment.
Best answer 5 votes 5 votes In Synchronous counter , all the flip-flops change their states at the same time. hence the maximum possible time neeeded is 15 ns. Bikram answered Feb 6, 2017 selected Feb 6, 2017 by Bikram Bikram comment Share Follow See all 2 Comments See all 2 2 Comments reply amitqy commented Nov 3, 2018 reply Follow Share what does "same time" mean ? they change their state at same time instant or they all take same time but do not change simultaneouly 0 votes 0 votes KUSHAGRA गुप्ता commented Sep 21, 2019 reply Follow Share Sir, while i was reading about synchronous counters i came across two formulas: The total delay for synchronous series counter: $T_{clk}\geqslant t_{pd}+(n-2)t_{pd} \ [AND\ gate]$ The total delay for synchronous parallel carry counter: $T_{clk}\geqslant t_{pd}+t_{pd} \ [AND\ gate]$ Sir Please help me out as why these formulas might not be valid. Thankyou. 0 votes 0 votes Please log in or register to add a comment.
2 votes 2 votes In synchronous counters, the clock input is given to all the FFs at the same time. So, all the FFs begin their operations at the same time, and hence end them at the same time. In 15ns all the FFs would change their respective states parallelly. JashanArora answered Dec 26, 2019 JashanArora comment Share Follow See all 0 reply Please log in or register to add a comment.
0 votes 0 votes @Bikram Sir,please suggest some solution ukn answered Feb 6, 2017 ukn comment Share Follow See 1 comment See all 1 1 comment reply Bikram commented Feb 6, 2017 reply Follow Share @ukn please read my answer. 0 votes 0 votes Please log in or register to add a comment.