The Gateway to Computer Science Excellence
+3 votes
716 views

Provide short answers to the following questions:

Explain the behaviour of the following logic circuit (Fig.4) with level input A and output B

in Digital Logic by Boss (30.2k points) | 716 views
+5

1st NAND gate = $\overline{(A\cdot B)}$
then NOT = $A\cdot B$

2nd NOT = $\overline{A}$

then NOR = $\overline{(A\cdot B)+\overline{A}} = \overline{B+\overline{A}} = A \cdot \overline{B}$

this shows 
when A = 0  output is 0
when A = 1 output is toggled i.e, 
$\overline{B}$

correct me if i m wrong??

0
You are treating it as a combinational ckt. U didnt account for the feedback of the output .
0
Please, someone, explain this question in brief.

2 Answers

+1 vote
This is a sequential Ckt not a combinational one, therefore solving using just input var doesnt yeilds correct output.

First we need to simplify the ckt.

The two not gates at the input end of the nor gate can be combined with the gate to get : (A'+B')' = AB

Now, since we have two Vars we will have 4 combinations 00 01 10 11

On analysinh each we will see that for every combination where

A = 0 we have the stable output of 0

A=1 we will have a RACE condition.
by Active (2.3k points)
0 votes

There is a NOT after NAND i,e. It is AND.

So it will be A.B

and other side : $\bar{A}$

after NORING $\overline{AB+\overline{A}}$

$\overline{AB} + \overline{\overline{A}}$

$\bar{A} + \bar{B} + A = 1$

So Answer is 1.

by Active (4.6k points)
edited by
0
Same mistake as above.

Treating a sequential ckt as combinational. Your answer is correct if it had been a combinational ckt just dependent on inputs for all cycles.

Related questions

Quick search syntax
tags tag:apple
author user:martin
title title:apple
content content:apple
exclude -tag:apple
force match +apple
views views:100
score score:10
answers answers:2
is accepted isaccepted:true
is closed isclosed:true
50,647 questions
56,492 answers
195,439 comments
100,707 users