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A certain computer system was designed with cache memory of size $1$ Kbytes and main memory size of $256$ Kbytes. The cache implementation was fully associative cache with $4$ bytes per block. The CPU memory data path was $16$ bits and the memory was $2-$way interleaved. Each memory read request presents two $16-$bit words. A program with the model shown below was run to evaluate the cache design.

 

Answer the following questions:

  1. What is the hit ratio?
  2. Suggest a change in the program size of model to improve the hit ratio significantly.
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Total number of block access $= (512/4+100\times 1028/4+ 512/4)=25956$

All the blocks above and below the loop region can be assumed to be cache misses.

It is given that the cache is fully associative but the replacement policy is not mentioned. Let's assume it is $\text{FIFO}.$ Also, for simplicity let's assume that there's no reuse within a cache block.

In the first loop access every cache access will be a miss. Since the loop body size is $1028$ and we assumed $\text{FIFO},$ the last cache block will replace the first one. In the second iteration, first cache block access will be a miss and this will replace the second cache block. Going like this every cache block access will be a miss.

(i) So, hit ratio $=0.$

(ii) By just reducing the loop body size by $4$ bytes, all the loop accesses from second iteration of the loop will be a hit. So, we can get a hit ratio of $\frac{99\times 1024}{101\times 1024}= 98.01\%$
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