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You are given a free running clock with a duty cycle of $50\%$ and a digital waveform $f$ which changes only at the negative edge of the clock. Which one of the following circuits (using clocked D flip-flops) will delay the phase of $f$ by $180°$?

@chottu isn't the phase difference for option b, 90 deg ?
i think in explanation with waveforms a is wrongly solved......and phase shift in a is 90 not 270

YES, @ Even I think there is a problem in option B too.

Ans- C.

we can check the options for which output is f’ as it is asked about 180degree duty  cycle even by that i get the answer is there any wrong in my approach
The FF is positive edge triggered.

Also for optin A, waveform changes exactly when clock changes, which causes confusion that option A is correct.

It's worth to remember 👍

B and D are inverting f and hence cannot be the answer.

In A, the output is activated by CLK on the final D flip flop. So, the output will have the same phase as f.

In C, the output is activated by CLK', and since CLK is having 50% duty cycle, this should mean the output will now have a phase difference of 180 degrees.
by

@arjun sir

In A, the output is activated by CLK on the final D flip flop. So, the output will have the same phase as f.

can't get these line
edited

@Arjun sir, what does phase delay by 180 means?

Also ,when f changes on negative clock then how can d change on same clock?The updated value of F will be available to D on next clock cycle  as in https://gateoverflow.in/264/gate2005-62 ?

Thank you for this short and beautiful analysis

Explanation: We assume the D flip-flop to be negative edge triggered.

In option (A), during the negative edge of the clock, first flip-flop inverts complement of ‘f’. But, the output of first flip-flop has the same phase as ‘f’. Now, we give this output as input to the second flip-flop, which is enabled by ‘clk’.

Thus, we get a double inverted output having same phase as the input. So, A is not the correct option.

In option (B) and (D), the output is inverted ‘f’. But, we want ‘f’ as the output.
So, (B) and (D) can’t be the answer.

In option (C), the first flip-flop is activated by ‘clk’. So, the output of first flip-flop has the same phase as ‘f’. But, the second flip-flop is enabled by complement of ‘clk’. Since the clock ‘clk’ has a duty cycle of 50% , we get the output having phase delay of 180 degrees.

Therefore, (C) is the correct answer.

Sir, can u please explain with a timing diagram of each option.. and what is duty cycle of 50% mean here
i am also not getting what is meant by 50 percent duty cycle here?

The inverter at f, and Q' will flip the waveform.
The inverter at CLK will delay the waveform.

Option B flips waveform via an inverter at f.

Option D flips waveform via making it pass through Q'.

So, these both can't be the answer.

In Option A, we delay however much we want in the beginning, but the output of the first FF will supply a continuous stream of waveform to the second FF. And, the second FF is "in sync" with CLK. Since only inverted CLK can delay the waveform here, and we don't have it at the second FF, we don't get any delay.

In Option C, we don't delay at all through the first FF. But at second FF, we invert the CLK, which delays the output waveform. By how much would it be delayed? Since the duty cycle is 50%, well get a delay of 50% of 360° => 180°.

Option C.