You are given a free running clock with a duty cycle of $50\%$ and a digital waveform $f$ which changes only at the negative edge of the clock. Which one of the following circuits (using clocked D flip-flops) will delay the phase of $f$ by $180°$?

### 14 Comments

**To understand what is duty cycle??**

https://en.wikipedia.org/wiki/Duty_cycle#/media/File:PWM_duty_cycle_with_label.gif

**What is phase delay of 180 degrees??**

The two waves are said to have a phase of 180 degrees if they are mirror image of each other

for e.g.

Duty Cycle - https://en.wikipedia.org/wiki/Duty_cycle (Observe Diagram)

50% means 1(Up) and 0(Down) period is equal.

Important Line ->

digital waveform f which changes only at the negative edge of the clock

changes only at the negative edge of the clock does not means it always changes.

@gari ji ,

why did you remove [email protected] i think your explanation was precise.

OK adding again.

ping @VS, @shraddha_gami, @Puja Mishra, @srestha @Pronomita Dey 1 @iarnav and @Aaditya Pundir ji

## 5 Answers

### 25 Comments

I have a doubt that 50% duty cycle would mean that after getting output from first FF the wave is shifted by half the clock.... So when this is input to the second FF and output is generated... Will the output wave again shifted by half clock period..?? From your answer I mean that u shifted only once, the first time....

In A, the output is activated by CLK on the final D flip flop. So, the output will have the same phase as f.

In C, the output is activated by CLK', and since CLK is having 50% duty cycle, this should mean the output will now have a phase difference of 180 degrees.

### 9 Comments

Plz correct me if I'm wrong.

Now for A case, the output of first flip flop given to the next one is same as f due to double inversion. But is it of same phase? Also if a waveform is passed through a D flip flop using a clock which is in sync with the waveform, phase change happens?

I also got the same timing diagram except for the final output where I took the FF as negative edge triggered.

" as per the notation used in the diagram, the first flip flop works at the negative level of the clock whereas the second flip flop works at the positive level of the clock"

Do you have a reference for this notion?

I read that in a book. A bubble is used along with a triangle to signify negative edge triggered. A normal line implies level triggered. You can see the notations here:

http://www.circuitstoday.com/triggering-of-flip-flops

Even if the flip flops are negative edge triggered, I think the final output must not change. If the first flip flop works on negative edge of the clock, the second flip flop will actually work on the positive edge of the original clock (or negative edge of the inverted clock); since the clock is inverted in the second flip flop.

really confusing though! :P

We know that,

1. Final DFF needs to trigger at the same clock edge as f, to be in a 180 phase. Hence second DFF gets neg, and first gets positive. (options A and D are out)

2. If you draw the timing diagram, value of f from previous clock needs to be passed down to final DFF. This can be done by i) initial DFF taking neg_f and and final DFF taking neg_D0 as input, or ii) initial DFF taking f and and final DFF taking D0 as input. This eliminates option B.

Hence C is the answer

@Arjun sir, what does phase delay by 180 means?

Also ,when f changes on negative clock then how can d change on same clock?The updated value of F will be available to D on next clock cycle as in https://gateoverflow.in/264/gate2005-62 ?

**Explanation:** We assume the D flip-flop to be negative edge triggered.

In option (A), during the negative edge of the clock, first flip-flop inverts complement of ‘f’. But, the output of first flip-flop has the same phase as ‘f’. Now, we give this output as input to the second flip-flop, which is enabled by ‘clk’.

Thus, we get a double inverted output having same phase as the input. So, A is not the correct option.

In option (B) and (D), the output is inverted ‘f’. But, we want ‘f’ as the output.

So, (B) and (D) can’t be the answer.

In option (C), the first flip-flop is activated by ‘clk’. So, the output of first flip-flop has the same phase as ‘f’. But, the second flip-flop is enabled by complement of ‘clk’. Since the clock ‘clk’ has a duty cycle of 50% , we get the output having phase delay of 180 degrees.

Therefore, (C) is the correct answer.

The inverter at f, and Q' will flip the waveform.

The inverter at CLK will delay the waveform.

Option B flips waveform via an inverter at f.

Option D flips waveform via making it pass through Q'.

So, these both can't be the answer.

In Option A, we delay however much we want in the beginning, but the output of the first FF will supply a continuous stream of waveform to the second FF. And, the second FF is "in sync" with CLK. Since only inverted CLK can delay the waveform here, and we don't have it at the second FF, we don't get any delay.

In Option C, we don't delay at all through the first FF. But at second FF, we invert the CLK, which delays the output waveform. By how much would it be delayed? Since the duty cycle is 50%, well get a delay of 50% of 360° => 180°.

**Option C.**

Key lies in noting that there is a 90° phase lag -

1. between f and output of FF1 if it is positive edge triggered, since f changes for every negative edge.

2. between the two FFs as one is positive edge triggered and the other is negative edge triggered.

So,

A. FF1 output = ((f')') = f and FF2 output = f$\angle$ 90°

B. FF1 output = f'$\angle$ 90° and FF2 output = f'$\angle$ 180° = f (since f is a periodic digital signal with 50% duty cycle)

C. FF1 output = f$\angle$ 90° and FF2 output = f$\angle$ 180°

D. FF1 output = f' and FF2 output = f'$\angle$ 90°

This explains the timing diagrams and @Arjun sir's answer.