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70 votes
70 votes

You are given a free running clock with a duty cycle of $50\%$ and a digital waveform $f$ which changes only at the negative edge of the clock. Which one of the following circuits (using clocked D flip-flops) will delay the phase of $f$ by $180°$?

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4 Comments

@chottu isn't the phase difference for option b, 90 deg ?
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i think in explanation with waveforms a is wrongly solved......and phase shift in a is 90 not 270
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YES, @ Even I think there is a problem in option B too.

 

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5 Answers

53 votes
53 votes

Ans- C.

 

edited by

4 Comments

we can check the options for which output is f’ as it is asked about 180degree duty  cycle even by that i get the answer is there any wrong in my approach
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The FF is positive edge triggered.

Also for optin A, waveform changes exactly when clock changes, which causes confusion that option A is correct.
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It's worth to remember 👍

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17 votes
17 votes
B and D are inverting f and hence cannot be the answer.

In A, the output is activated by CLK on the final D flip flop. So, the output will have the same phase as f.

In C, the output is activated by CLK', and since CLK is having 50% duty cycle, this should mean the output will now have a phase difference of 180 degrees.
by

11 Comments

Though I am also getting the answer to be (c), I have a doubt in your explanation. As per the question, f changes only at the negative edge of the clock. So, the time period of f is twice that of the clock. In option (a), during the negative clock, the first Flipflop inverts the complement of f (since the output is taken from ~Q (Q bar),).Hence the output phase is same as f. But the next flipflop delays it by half clock. So, f suffers a delay of 90 degrees in the second Flipflop. So, the output in option (a) does not have the same phase as f, but it is delayed by 90 degrees.

Plz correct me if I'm wrong.
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I must have added I assumed negative edge triggered flip flop.

Now for A case, the output of first flip flop given to the next one is same as f due to double inversion. But is it of same phase? Also if a waveform is passed through a D flip flop using a clock which is in sync with the waveform, phase change happens?
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edited by

As far as I know, double inversion doesn't change phase.

Also note that as per the notation used in the diagram, the first flip flop works at the negative level of the clock whereas the second flip flop works at the positive level of the clock.

I am attaching the timing diagram for option (a).

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I also got the same timing diagram except for the final output where I took the FF as negative edge triggered. 

" as per the notation used in the diagram, the first flip flop works at the negative level of the clock whereas the second flip flop works at the positive level of the clock"

Do you have a reference for this notion?

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I read that in a book. A bubble is used along with a triangle to signify negative edge triggered. A normal line implies level triggered. You can see the notations here:

http://www.circuitstoday.com/triggering-of-flip-flops

Even if the flip flops are negative edge triggered, I think the final output must not change. If the first flip flop works on negative edge of the clock, the second flip flop will actually work on the positive edge of the original clock (or negative edge of the inverted clock); since the clock is inverted in the second flip flop.

really confusing though! :P

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your final o/p is not correct. You are taking Q from first FF to be given as an i/p to second FF but actually it is Q' .
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We know that,

1. Final DFF needs to trigger at the same clock edge as f, to be in a 180 phase. Hence second DFF gets neg, and first gets positive. (options A and D are out)

2. If you draw the timing diagram, value of f from previous clock needs to be passed down to final DFF. This can be done by i) initial DFF taking neg_f and and final DFF taking neg_D0 as input, or ii) initial DFF taking f and and final DFF taking D0 as input. This eliminates option B.

Hence C is the answer

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@arjun sir

In A, the output is activated by CLK on the final D flip flop. So, the output will have the same phase as f.

can't get these line
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edited by

@Arjun sir, what does phase delay by 180 means?

Also ,when f changes on negative clock then how can d change on same clock?The updated value of F will be available to D on next clock cycle  as in https://gateoverflow.in/264/gate2005-62 ?

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Thank you for this short and beautiful analysis
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@Arjun Sir, can you please share any counter resource because I am really confused as to interpret counters, like when it will be activated or the final output phase. Please

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8 votes
8 votes

Explanation: We assume the D flip-flop to be negative edge triggered.

 
In option (A), during the negative edge of the clock, first flip-flop inverts complement of ‘f’. But, the output of first flip-flop has the same phase as ‘f’. Now, we give this output as input to the second flip-flop, which is enabled by ‘clk’.

Thus, we get a double inverted output having same phase as the input. So, A is not the correct option.

In option (B) and (D), the output is inverted ‘f’. But, we want ‘f’ as the output.
So, (B) and (D) can’t be the answer.

In option (C), the first flip-flop is activated by ‘clk’. So, the output of first flip-flop has the same phase as ‘f’. But, the second flip-flop is enabled by complement of ‘clk’. Since the clock ‘clk’ has a duty cycle of 50% , we get the output having phase delay of 180 degrees.

 
Therefore, (C) is the correct answer.

3 Comments

Sir, can u please explain with a timing diagram of each option.. and what is duty cycle of 50% mean here
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i am also not getting what is meant by 50 percent duty cycle here?
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We assume the D flip-flop to be negative edge triggered

it is given in question itself. 

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4 votes
4 votes

The inverter at f, and Q' will flip the waveform.
The inverter at CLK will delay the waveform.

Option B flips waveform via an inverter at f.

Option D flips waveform via making it pass through Q'.

So, these both can't be the answer.

 

In Option A, we delay however much we want in the beginning, but the output of the first FF will supply a continuous stream of waveform to the second FF. And, the second FF is "in sync" with CLK. Since only inverted CLK can delay the waveform here, and we don't have it at the second FF, we don't get any delay.

In Option C, we don't delay at all through the first FF. But at second FF, we invert the CLK, which delays the output waveform. By how much would it be delayed? Since the duty cycle is 50%, well get a delay of 50% of 360° => 180°.

Option C.

Answer:

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