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70 votes
70 votes

You are given a free running clock with a duty cycle of $50\%$ and a digital waveform $f$ which changes only at the negative edge of the clock. Which one of the following circuits (using clocked D flip-flops) will delay the phase of $f$ by $180°$?

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4 Comments

@chottu isn't the phase difference for option b, 90 deg ?
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i think in explanation with waveforms a is wrongly solved......and phase shift in a is 90 not 270
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YES, @ Even I think there is a problem in option B too.

 

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5 Answers

53 votes
53 votes

Ans- C.

 

edited by

25 Comments

How you created these waveforms?

I also tried but I am getting different waveforms.

Can you explain anyone of the waveforms only,rest I will do accordingly.

Thanks in advance :)
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Actually I draw these waveform according to the output of 2nd D-FF.
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That's ok:)

See where I am getting confused is ::
1) Somewhere taking f and some where f complement (that can be managed)

2) Which FF is taken as which edge triggered ?( causing confusion)

3) What is the significance of negating the clock?
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Negating a FF clock means that particular FF only become active during a negative clock edge and remain deactive during a positive colck edge.
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Please point out my mistake ::

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FF2 become active when first negative edge occurs and it will take output of FF1 as Input.

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But , final waveform and waveform of F are same .. Aren't they ? See from second clock cycle.

Also note Arjun sir's comment below :

B and D are inverting f and hence cannot be the answer.

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these are same from 2 clock cycle not from beginning. But we want exact same signal as F with 180 dealy.

OK.. apply F from 2nd clock cycle....Is there any difference..?? No... output is still same as above.

Inverting means same as F' not F.
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Got it !! Thanx :)

One last thing how to calculate the phase difference?

One more thing is there a shortcut method for this or we have to draw all waveforms always?
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Can you please check the waveform of option a.I think it should be 90 deg delay by F' and not F.Since for 2nd Flip flop input is Q' of first flip flop.

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Aaditya Pundir

In option a

when the f' changes at negative clock signal then at the same time the D flip flop also changing? first flip flop should read the value of f' in the previous cycle instead of new as new change should be available at end of clock?

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@Aaditya

I have a doubt that 50% duty cycle would mean that after getting output from first FF the wave is shifted by half the clock.... So when this is input to the second  FF and output is generated... Will the output wave again shifted by half clock period..?? From your answer I mean that u shifted only once, the first time....
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I have a doubt regarding A waveform drawn.Please visit my last comment.I think it will get high at positive edge of 3rd clock. @VS can you please check
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In option C)

Input of first FF is "F" so when first time we provide +ve edge then output of FF1 should be high till next +ve edge, and then low and continueu like this way. But you are taking Output of FF1 low. why??
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how are you deciding from which clock cycle to start?  I get it that C is producing same wave as F, but how and why is it starting from 2nd clock cycle?
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in option B, output of right FF is in phase 180 degree with complement of F right?

@Aaditya Pundir

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@aditi19

how?? Can u explain a bit more??

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@srestha

draw the waveform diagram

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@aditi19

Is it not same as F with $180^{o}$ delay??

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@srestha

in which option?

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@aditi19

I mean in B) there are only a delay of $180^{0}$

and each clock has a duty cycle of $50$%

Also I can see , it is a master-slave D-FF.

right??

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yes so?
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we can check the options for which output is f’ as it is asked about 180degree duty  cycle even by that i get the answer is there any wrong in my approach
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The FF is positive edge triggered.

Also for optin A, waveform changes exactly when clock changes, which causes confusion that option A is correct.
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It's worth to remember 👍

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17 votes
17 votes
B and D are inverting f and hence cannot be the answer.

In A, the output is activated by CLK on the final D flip flop. So, the output will have the same phase as f.

In C, the output is activated by CLK', and since CLK is having 50% duty cycle, this should mean the output will now have a phase difference of 180 degrees.
by

4 Comments

edited by

@Arjun sir, what does phase delay by 180 means?

Also ,when f changes on negative clock then how can d change on same clock?The updated value of F will be available to D on next clock cycle  as in https://gateoverflow.in/264/gate2005-62 ?

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Thank you for this short and beautiful analysis
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@Arjun Sir, can you please share any counter resource because I am really confused as to interpret counters, like when it will be activated or the final output phase. Please

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8 votes
8 votes

Explanation: We assume the D flip-flop to be negative edge triggered.

 
In option (A), during the negative edge of the clock, first flip-flop inverts complement of ‘f’. But, the output of first flip-flop has the same phase as ‘f’. Now, we give this output as input to the second flip-flop, which is enabled by ‘clk’.

Thus, we get a double inverted output having same phase as the input. So, A is not the correct option.

In option (B) and (D), the output is inverted ‘f’. But, we want ‘f’ as the output.
So, (B) and (D) can’t be the answer.

In option (C), the first flip-flop is activated by ‘clk’. So, the output of first flip-flop has the same phase as ‘f’. But, the second flip-flop is enabled by complement of ‘clk’. Since the clock ‘clk’ has a duty cycle of 50% , we get the output having phase delay of 180 degrees.

 
Therefore, (C) is the correct answer.

3 Comments

Sir, can u please explain with a timing diagram of each option.. and what is duty cycle of 50% mean here
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i am also not getting what is meant by 50 percent duty cycle here?
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We assume the D flip-flop to be negative edge triggered

it is given in question itself. 

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4 votes
4 votes

The inverter at f, and Q' will flip the waveform.
The inverter at CLK will delay the waveform.

Option B flips waveform via an inverter at f.

Option D flips waveform via making it pass through Q'.

So, these both can't be the answer.

 

In Option A, we delay however much we want in the beginning, but the output of the first FF will supply a continuous stream of waveform to the second FF. And, the second FF is "in sync" with CLK. Since only inverted CLK can delay the waveform here, and we don't have it at the second FF, we don't get any delay.

In Option C, we don't delay at all through the first FF. But at second FF, we invert the CLK, which delays the output waveform. By how much would it be delayed? Since the duty cycle is 50%, well get a delay of 50% of 360° => 180°.

Option C.

Answer:

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