in Digital Logic edited by
18,312 views
70 votes
70 votes

You are given a free running clock with a duty cycle of $50\%$ and a digital waveform $f$ which changes only at the negative edge of the clock. Which one of the following circuits (using clocked D flip-flops) will delay the phase of $f$ by $180°$?

in Digital Logic edited by
18.3k views

14 Comments

Anyone please give explanation. Should I draw timing diagrams and find the correct answer? @Arjun Sir,Please help
0
0
Please do !! I am getting (A) as answer. According to me (c) results in phase shift by 360 degree. Since the function changes only at negative edges of clock, that change , in option(c), will be reflected at the output only in next negative clock pulse. So it takes entire clock cycle which means 360 degree phase shift. While in option (A) change in function at negative edge of clock is reflected in the next positive edge of clock which means change is reflected in just half clock pulse. So this shifts by 180 degree. But answer is given (C). I am not able to figure out what I am lacking in. Please clarify.
5
5
I also have very same doubt. Please reply me if u got it cleared !!
0
0
edited by

To understand what is duty cycle??

https://en.wikipedia.org/wiki/Duty_cycle#/media/File:PWM_duty_cycle_with_label.gif

What is phase delay of 180 degrees??

The two waves are said to have a phase of 180 degrees if they are mirror image of each other

for e.g.

example

14
14
edited by

Duty Cycle - https://en.wikipedia.org/wiki/Duty_cycle (Observe Diagram)

50% means 1(Up) and 0(Down) period is equal.

Important Line ->

digital waveform f which changes only at the negative edge of the clock

changes only at the negative edge of the clock does not means it always changes.

1
1
edited by
why did you remove ...@chhotu.. i think your explanation was precise
0
0

@gari ji ,

why did you remove ...@chhotu.. i think your explanation was precise.

OK adding again.

ping @VS, @shraddha_gami, @Puja Mishra, @srestha @Pronomita Dey 1 @iarnav and @Aaditya Pundir ji

15
15

phase in digital signals

Phase is just shifting of signal, and inversion is defined as complement of f. so option (B) and (D) are rejected.

Drawing the output response of the rest of options will clearify that answer is (C) which has 180 phase difference.

1
1
For 1st flip flop in option( a) if f is 0 and clock is o then what will be the Qbar
0
0
How did you draw this timing graphs
0
0
can anyone provide the resource for this type of problems

??
0
0
@chottu isn't the phase difference for option b, 90 deg ?
0
0
i think in explanation with waveforms a is wrongly solved......and phase shift in a is 90 not 270
0
0

YES, @ Even I think there is a problem in option B too.

 

0
0

5 Answers

53 votes
53 votes

Ans- C.

 

edited by

4 Comments

we can check the options for which output is f’ as it is asked about 180degree duty  cycle even by that i get the answer is there any wrong in my approach
0
0
The FF is positive edge triggered.

Also for optin A, waveform changes exactly when clock changes, which causes confusion that option A is correct.
0
0

It's worth to remember 👍

4
4
17 votes
17 votes
B and D are inverting f and hence cannot be the answer.

In A, the output is activated by CLK on the final D flip flop. So, the output will have the same phase as f.

In C, the output is activated by CLK', and since CLK is having 50% duty cycle, this should mean the output will now have a phase difference of 180 degrees.
by

4 Comments

edited by

@Arjun sir, what does phase delay by 180 means?

Also ,when f changes on negative clock then how can d change on same clock?The updated value of F will be available to D on next clock cycle  as in https://gateoverflow.in/264/gate2005-62 ?

0
0
Thank you for this short and beautiful analysis
0
0

@Arjun Sir, can you please share any counter resource because I am really confused as to interpret counters, like when it will be activated or the final output phase. Please

0
0
8 votes
8 votes

Explanation: We assume the D flip-flop to be negative edge triggered.

 
In option (A), during the negative edge of the clock, first flip-flop inverts complement of ‘f’. But, the output of first flip-flop has the same phase as ‘f’. Now, we give this output as input to the second flip-flop, which is enabled by ‘clk’.

Thus, we get a double inverted output having same phase as the input. So, A is not the correct option.

In option (B) and (D), the output is inverted ‘f’. But, we want ‘f’ as the output.
So, (B) and (D) can’t be the answer.

In option (C), the first flip-flop is activated by ‘clk’. So, the output of first flip-flop has the same phase as ‘f’. But, the second flip-flop is enabled by complement of ‘clk’. Since the clock ‘clk’ has a duty cycle of 50% , we get the output having phase delay of 180 degrees.

 
Therefore, (C) is the correct answer.

3 Comments

Sir, can u please explain with a timing diagram of each option.. and what is duty cycle of 50% mean here
2
2
i am also not getting what is meant by 50 percent duty cycle here?
0
0

We assume the D flip-flop to be negative edge triggered

it is given in question itself. 

0
0
4 votes
4 votes

The inverter at f, and Q' will flip the waveform.
The inverter at CLK will delay the waveform.

Option B flips waveform via an inverter at f.

Option D flips waveform via making it pass through Q'.

So, these both can't be the answer.

 

In Option A, we delay however much we want in the beginning, but the output of the first FF will supply a continuous stream of waveform to the second FF. And, the second FF is "in sync" with CLK. Since only inverted CLK can delay the waveform here, and we don't have it at the second FF, we don't get any delay.

In Option C, we don't delay at all through the first FF. But at second FF, we invert the CLK, which delays the output waveform. By how much would it be delayed? Since the duty cycle is 50%, well get a delay of 50% of 360° => 180°.

Option C.

Answer:

Related questions