GATE CSE 2003 | Question: 10, ISRO-DEC2017-41
in CO and Architecture edited by
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For a pipelined CPU with a single ALU, consider the following situations

  1. The ${j+1}^{st}$ instruction uses the result of the $j^{th}$ instruction as an operand

  2. The execution of a conditional jump instruction

  3. The $j^{th}$ and ${j+1}^{st}$ instructions require the ALU at the same time.

Which of the above can cause a hazard

  1. I and II only
  2. II and III only
  3. III only
  4. All the three
in CO and Architecture edited by
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4 Answers

56 votes
 
Best answer

1. Data hazard
2. Control hazard
3. Structural hazard as only one ALU is there

So, $(D)$. 

http://www.cs.iastate.edu/~prabhu/Tutorial/PIPELINE/hazards.html

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3 Comments

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@Arjun sir if the question says must cause a stall in the pipeline then the answer will be C?
0

 I believe all are hazardous.

0
but data hazard can be solved by operand forwarding.
0
0 votes
Answer is D

I . Read before write (data hazard)

II. control hazard

III. Structural hazard.

1 comment

the point number 1, that’s a RAW (Read after Write Hazard) my dear.
1
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–2 votes
Hazards in pipelining occur due to sync ,interrupts,branching,raw timings and all three have one or the other problem so they shouldnt be pipelined option d.
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